PICkit™ 3 Starter Kit User’s Guide
DS41628B-page 80 2012 Microchip Technology Inc.
The addressing modes are:
1. Inherent
2. Literal
3. Direct
4. Indirect
3.12.3.1 INHERENT AND LITERAL
Many PIC device control instructions do not need any argument at all; they either
perform an operation that globally affects the device or they operate implicitly on one
register. This addressing mode is known as Inherent Addressing. Examples include
SLEEP and RESET, which are used in the EEPROM lesson.
Other instructions work in a similar way but require an additional explicit argument in
the opcode. This is known as Literal Addressing mode because they require some
literal value as an argument. Examples include addlw, movlb, call, and goto.
3.12.3.2 DIRECT ADDRESSING
Direct addressing specifies all or part of the source and/or destination address of the
operation within the opcode itself. The options are specified by the arguments
accompanying the instruction. In the core PIC device instruction set, bit-oriented and
byte-oriented instructions use some version of direct addressing by default. All of these
instructions include a 7-bit (8-bit for PIC18) literal address in their Least Significant
Byte. This address specifies either a register address in one of the banks of data RAM
or a location in the Access Bank (if using the PIC18) as the data source for the
instruction.
The destination of the operation’s results is determined by the destination bit ‘d’. When
‘d’ is ‘1’, the results are stored back in the source register, overwriting its original
contents. When ‘d’ is ‘0’, the results are stored in the WREG register.
3.12.3.3 INDIRECT ADDRESSING
Indirect addressing allows the user to access a location in data memory without giving
a fixed address in the instruction. This is done by using File Select Registers (FSRs)
as pointers to the locations which are to be read or written. Since the FSRs are
themselves located in RAM as Special File Registers, they can also be directly
manipulated under program control. This makes FSRs very useful in implementing
data structures, such as tables and arrays in data memory. The registers for indirect
addressing are also implemented with Indirect File Operands (INDFs) that permit
automatic manipulation of the pointer value with auto-incrementing, auto-decrementing
or offsetting with another value.
The INDFn registers are not physical registers. These can be thought of as “virtual”
registers: they are mapped in the SFR space, but are not physically implemented.
Reading or writing to a particular INDF register actually accesses its corresponding
FSR register pair. A read from INDF1, for example, reads the data at the address
indicated by FSR1H:FSR1L.
To Next Page
Loading...
Need help?
General
