APPENDICES APPENDIX
Appendix 5 Operation Image and Data Structure of Predefined Protocol
525
A
■Error completion (receive wait timeout error)
• When variables are included in receive packet elements, variable parts are not verified.
• When more than one receive packet is specified, received data is verified with the receive packet
information of the first registered packet in the order of registration. The receive processing is performed
once received data match one of the receive packet number, and further verification is not performed.
• The receive packet number which is matched as the result of the verification is stored in the control data of
the dedicated instruction (CPRTCL instruction).
Error occurred
CPU
module
Execute dedicated instruction
(G(P).CPRTCL)
Completion device
ON at abnormal
completion
Status display device
at completion
(Receive
buffer clear)
t: Reception waiting time
C24
* Only if it is specified
Send packet
Verification mismatch
Send packet
Receive packet Receive packet
Target device
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