Mitsubishi Electric MELSEC iQ-RJ71C24-R4 - Examples of Procedure for Data Communications with CPU Module; Sequential Data Communications between Target Devices and the CPU Module

18 DATA COMMUNICATIONS BETWEEN TARGET DEVICE AND CPU MODULE IN M:N BASIS
18.3 Examples of Procedure for Data Communications with CPU Module
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18.3 Examples of Procedure for Data Communications
with CPU Module
This section shows examples of procedures to communicate data with the CPU module by configuring interlocks among the
target devices.
Sequential data communications between target devices and the
CPU module
Each target device obtains the line ownership in turns according to the station number to communicate with the CPU module.
Ex.
Ex.
The example below shows the procedures for each target device to communicate data with the CPU module.
 When the system starts, the target device with the lowest station number (1BH) obtains the line ownership.
• When format 1, format 2, or format 4 is selected for communication using ASCII code, change ENQ (05H).
 The target device that obtained the line ownership,
• Begins the processing from  after communicating data with the CPU module within the maximum data communication
time arranged among the target devices, when communicating data with the CPU module.
• Immediately begins the processing from , when not communicating data with the CPU module.
 The target devices that have not obtained the line ownership check the line usage time of the target device that obtained
the line ownership and ignore the received data not addressed to their own station.
When the line usage time exceeds the maximum data communication time, each target device performs the processing of .
Time
Station No.
1BH
target device
Transmission to transfer
the line ownership
Response
Station No.
1CH
target device
Data communications
with the CPU module
Station No. (m-1)
target device
Ò ÔÔ
Ó-
Ô
a
CPU CPU CPU
C24 C24 C24 C24
CPU
Target device Target device Target device Target device
When communicating
data with the station
No. 1H CPU module
(Station No.:1BH) (Station No.:1CH) (Station No.:1DH) (Station No.:1EH)
(Station No.:0H)
(Station No.:15H)
(Station No.:2H)
(Station No.:1H)
: Target device that obtained the line ownership
The above C24 includes Q series C24, L series C24, QC24(N), and UC24.