Mitsubishi Electric Q13UDVCPU - Page 477

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APPENDICES
A
Appendix 2 List of Special Relay Areas
*1 Modules whose function version B or later
*2 The following modules support these areas:
• Universal model QCPU whose serial number (first five digits) is "10102" or later
• Q00UJCPU, Q00UCPU, Q01UCPU
*3 The following modules support this area:
• Universal model QCPU whose serial number (first five digits) is "10102" or later
• Q00UCPU, Q01UCPU
*4 Modules whose serial number (first five digits) is "07032" or later
*5 Modules whose serial number (first five digits) is "06082" or later
*6 Modules whose serial number (first five digits) is "07012" or later
*7 Modules whose serial number (first five digits) is "04012" or later
*8 Modules whose serial number (first five digits) is "05032" or later
*9 Universal model QCPU except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU
*10 Universal model QCPU except the Q00UJCPU
*11 Modules whose serial number (first five digits) is "12052" or later
*12 Modules whose serial number (first five digits) is "14072" or later
*13 Following modules except the Q00UJCPU, Q00UCPU, Q01UCPU, and Q02UCPU.
• Modules whose serial number (first five digits) is "14072" or later other than the High-speed Universal model
QCPU
• High-speed Universal model QCPU whose serial number (first five digits) is "16043" or later
*14 Modules whose serial number (first five digits) is "15102" or later
*15 Modules whose serial number (first five digits) is "16042" or later
*16 Modules whose serial number (first five digits) is "16043" or later
*17 Modules whose serial number (first five digits) is "16112" or later
SM796
Block information
using the multiple
CPU high-speed
transmission
dedicated
instruction (for
CPU No.1)
OFF: Block is secured
ON: Block set by
SD796 cannot be
secured
This relay turns on when the number of
the remaining blocks in the dedicated
instruction transmission area used for the
multiple CPU high-speed transmission
dedicated instruction (target CPU= CPU
No.1) is less than the number of blocks
specified in SD796. This relay is on when
an instruction is executed, and is off while
an END processing is being executed or
when free space is available in the area.
S
(Instruction
execution/
Every END
processing)
New
QnU
*9
SM797
Block information
using the multiple
CPU high-speed
transmission
dedicated
instruction (for
CPU No.2)
OFF: Block is secured
ON: Block set by
SD797 cannot be
secured
This relay turns on when the number of
the remaining blocks in the dedicated
instruction transmission area used for the
multiple CPU high-speed transmission
dedicated instruction (target CPU= CPU
No.2) is less than the number of blocks
specified in SD797. This relay is on when
an instruction is executed, and is off while
an END processing is being executed or
when free space is available in the area.
S
(Instruction
execution/
Every END
processing)
New
QnU
*9
SM798
Block information
using the multiple
CPU high-speed
transmission
dedicated
instruction (for
CPU No.3)
OFF: Block is secured
ON: Block set by
SD796 cannot be
secured
This relay turns on when the number of
the remaining blocks in the dedicated
instruction transmission area used for the
multiple CPU high-speed transmission
dedicated instruction (target CPU= CPU
No.3) is less than the number of blocks
specified in SD798. This relay is on when
an instruction is executed, and is off while
an END processing is being executed or
when free space is available in the area.
S
(Instruction
execution/
Every END
processing)
New
QnU
*9
SM799
Block information
using the multiple
CPU high-speed
transmission
dedicated
instruction (for
CPU No.4)
OFF: Block is secured
ON: Block set by
SD799 cannot be
secured
This relay turns on when the number of
the remaining blocks in the dedicated
instruction transmission area used for the
multiple CPU high-speed transmission
dedicated instruction (target CPU= CPU
No.) is less than the number of blocks
specified in SD799. This relay is on when
an instruction is executed, and is off while
an END processing is being executed or
when free space is available in the area.
S
(Instruction
execution/
Every END
processing)
New
QnU
*9
Number Name Meaning Explanation
Set by
(When Set)
Corresponding
ACPU
M9
Corresponding
CPU