Chapter 3
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33MHz. For example, if the Host clock is 133MHz, the
DRAM clock will be 100MHz.
HCLK+33M The DRAM clock will be equal to the Host clock plus
33MHz. For example, if the Host clock is 100MHz, the
DRAM clock will be 133MHz.
Memory Hole
In order to improve performance, certain space in memory can be reserved
for ISA peripherals. This memory must be mapped into the memory space
below 16MB. When this area is reserved, it cannot be cached. The settings
are 15M-16M and Disabled (default).
P2C/C2P Concurrency
This field enables or disables the PCI to CPU and CPU to PCI concurrency
feature, which allows synchronous data transmission from PCI to CPU and
vice versa. Selecting the default Enabled will increase system performance.
Fast R-W Turn Around
This is used to control the fast read/write turn around feature for DRAM
timing. Settings are Enabled and Disabled (default). Enabled improves
system performance while Disabled provides stability.
System BIOS Cacheable
System BIOS ROM at F0000h-FFFFFh is always copied to RAM for faster
execution. Selecting Enabled allows the contents of F0000h RAM memory
segment to be written to and read from cache memory, resulting in better
system performance. However, if any program writes to this memory area, a
system error may result. The settings are Enabled and Disabled (default).
Video RAM Cacheable
The field allows the caching of video memory, resulting in increased system
performance. Settings are Enabled and Disabled (default).
AGP Aperture Size
Selects the size of the Accelerated Graphics Port (AGP) aperture. Aperture
is a portion of the PCI memory address range dedicated for graphics memory
address space. Host cycles that hit the aperture range are forwarded to the
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