Chapter 3
3-16
detected, the onboard MC97 modem controller will be enabled; if not, the
controller is disabled. Disable the controller if you want to use other
controller cards to connect modems. Settings are Auto (default) and
Disabled.
CPU to PCI Write Buffer
When Enabled, CPU can write up to four words of data into the PCI write
buffer before the CPU must wait for PCI bus cycles to finish. When
Disabled, the CPU must wait after each write cycle until the PCI bus signals
that it is ready to receive more data.
PCI Dynamic Bursting
When Enabled, every write transaction goes to the write buffer. Then
burstable transactions burst on the PCI bus and nonburstable transactions
do not.
PCI Master 0 WS Write
When Enabled, writes to the PCI bus are executed with zero wait state.
Default is Enabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delay
transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1. Default is Enabled.
PCI #2 Access #1 Retry
When Disabled, PCI#2 will not be disconnected until access finishes
(default). When Enabled, PCI#2 will be disconnected if max retries are
attempted without success. Default is Enabled.
AGP Master 1 WS Write
When Enabled, writes to the AGP bus are executed with one wait state
inserted. Default is Disabled.
AGP Master 1 WS Read
When Enabled, one wait state is inserted in the AGP read cycle. Default is
Disabled.
To Next Page
Loading...
