Chapter 4
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warded to the AGP without any translation.
AGP-4X Mode
This item is used to Enabled or Disabled the AGP support for AGP 4x
mode.
CPU to PCI Write Buffer
When this field is Enabled, writes from the CPU to the PCI bus are
buffered, to compensate for the differences between the CPU and the PCI
bus. When Disabled, the writes are not buffered and the CPU must wait
until the write is complete before starting another cycle.
PCI Dynamic Bursting
This item allows you to Enable or Disable the PCI dynamic bursting
function. The settings are Enabled or Disabled.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support
delay transactions cycles. Select Enabled to support compliance with PCI
specification version 2.1. The settings are Enabled or Disabled.
PCI#2 Access #1 Retry
When Disabled, PCI#2 will not be disconnected until access finishes
(default). When Enabled, PCI#2 will be disconnected if ms retries are
attempted without success.
AGP Master 1 WS Write
When Enabled, this item writes to the AGP (Accelerated Graphics
Port) are executed with one wait states.
AGP Master 1 WS Read
When Enabled, this item read to the AGP (Accelerated Graphics Port)
are executed with one wait states.
Memory Parity/ECC Check
This item when Enabled detects the memory parity and Error Check-
ing & Correcting. The settings are Enabled or Disabled.
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