BIOS Setup
PCI Master OWS Write
When Enabled, writes to the PCI bus are executed with zero wait state.
PCI Delay Transaction
The chipset has an embedded 32-bit posted write buffer to support delayed
transactions cycles so that transactions to and from the ISA bus are buffered
and PCI bus can perform other transactions while the ISA transaction is
underway. Select Enabled to support compliance with PCI specification ver-
sion 2.1. Setting options: Enabled, Disabled.
PCI #2 Access #1 Retry
When Disabled, PCI#2 will not be disconnected until access finishes.
When Enabled, PCI#2 will be disconnected if max retries are attempted
without success.
AGP Master 1WS Write
When Enabled, writes to the AGP bus are executed with one wait state
inserted.
AGP Master 1WS Read
When Enabled, one wait state is inserted in the AGP read cycle.
Memory Parity/ECC Check
Users can set the field to Enabled for memory checking if the type of DRAM
installed in your system is Parity or ECC (Error-Correcting Code) DRAM.
3-15
To Next Page
Loading...
