© National Instruments Corporation 9 NI 5761R User Guide and Specifications
Creating a LabVIEW Project and Run a VI on an FPGA Target
This section explains how to setup your target and create an FPGA VI and host VI for data
communication. For more detailed information about acquiring data on your NI 5761R, refer to the
example VIs available on your NI FlexRIO Adapter Module Support software.
Creating a Project
1. Launch LabVIEW, or if LabVIEW is already running, select File»New.
2. In the New dialog box, select Project»Empty Project. Click OK. The new project opens in the
Project Explorer window.
3. Save the project as
5761SampleAcq.lvproj.
Creating an FPGA Target VI
1. In the Project Explorer window, right-click My Computer and select New»Targets and
Devices.
2. In the Add Targets and Devices on My Computer dialog box, select the Existing Target or
Device option button and expand the FPGA Target. The target is displayed.
3. Select your device and click OK. The target and target properties are loaded into the project tree.
4. In the Project Explorer window, expand FPGA Target (RIOx, PXI-79xxR).
5. Right-click the FPGA target and select New»FPGA Base Clock.
6. In the Resource pull-down menu, select IO Module Clock 0.
7. Enter
125 MHz in the Compile for single frequency control. Click OK.
8. Right-click the FPGA target and select New»FPGA Base Clock again.
9. In the Resource pull-down menu, select 200 MHz Clock. Click OK.
10. Right-click IO Module and select Properties. In the General category, you can see the available
CLIP for the NI 5761 in the Component Level IP pane. If the category information is dimmed,
select the Enable IO Module checkbox.
11. Select NI 5761 Multi Sample CLIP.
12. In the Clock Selections category, select 200 MHz Clock from the pull-down menu for Clk200.
Leave Clk40 configured as the Top -Level Clock. This step is necessary to compile the FPGA
Target VI correctly. Click OK.
Note Configuring these clocks is required for proper CLIP operation. Refer to the NI 5761 CLIP
topics in the NI FlexRIO Help for more information about configuring your clocks.
13. In the Project Explorer window, right-click the FPGA target and select New»VI. A blank VI
opens.
14. Select Window»Show Block Diagram to open the VI block diagram.
15. In the Project Explorer window, expand the IO Module (NI 5761 : NI 5761) tree view.
16. Select AI 0 Data N and AI 0 Data N-1 and drag them onto the block diagram.
17. Add a Timed Loop around the two nodes.
18. Wire an indicator to the output terminals of the IO Module\AI 0 Data N and IO Module\AI 0
Data N-1 nodes.
19. Wire an FPGA Clock Constant to the input node of the Timed Loop. Set this constant to
IO Module Clock 0.
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