Chapter 7 Counters
© National Instruments 7-5 X Series User Manual
Buffered (Sample Clock) Edge Counting
With buffered edge counting (edge counting using a sample clock), the
counter counts the number of edges on the Source input after the counter is
armed. The value of the counter is sampled on each active edge of a sample
clock and stored in the FIFO. A DMA controller transfers the sampled
values to host memory.
The count values returned are the cumulative counts since the counter
armed event. That is, the sample clock does not reset the counter.
You can configure the counter to sample on the rising or falling edge of the
sample clock.
Figure 7-4 shows an example of buffered edge counting. Notice that
counting begins when the counter is armed, which occurs before the
first active edge on Sample Clock.
Figure 7-4. Buffered (Sample Clock) Edge Counting
Controlling the Direction of Counting
In edge counting applications, the counter can count up or down. You can
configure the counter to do the following:
• Always count up
• Always count down
•Count up when the Counter 0 B input is high; count down when it
is low
For information about connecting counter signals, refer to the Default
Counter/Timer Pinouts section.
3
6
3
Counter Armed
SOURCE
Sample Clock
(Sample on Rising Edge)
Counter Value
Buffer
1 0 7 6 3 4 5 2
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