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MSM85C154HVS
Oki MSM85C154HVS User Manual
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INTERNAL SPECIFICATIONS
153
Q
S
R
IE0 or 1
Q
D
L
INT
0 or
INT
1
PD
S3
RESET
S6
M END
PCON5(RPD)
PDRESET
S5
Figure 4-57 Power down cancellation circuit at INTERRUPT level input
S4
S2
S3
Q
S
L
R
IE0 or 1
PCON5(RPD)
PDRESET
D
Q
D
L
S3
D
L
S5
Q
PD
INT
0 or
INT
1
W TCON
BUS
RESET
Figure 4-58 Power down cancellation circuit at INTERRUPT edge input
159
161
Table of Contents
Default Chapter
3
Table of Contents
3
1 Introduction
8
MSM80C154S/MSM83C154S/MSM85C154HVS Outline
10
MSM80C154S/MSM83C154S Features
12
Additional Features in MSM80C154S/MSM83C154S/MSM85C154HVS
14
2 System Configuration
16
MSM80C154S/MSM83C154S/MSM85C154HVS Logic Symbols
18
MSM80C154S/MSM83C154S Pin Layout
19
MSM80C154S/MSM83C154S External Dimensions
22
MSM85C154HVS Pin Layout and External Dimensions
24
MSM80C154S Block Diagram
25
MSM83C154S Block Diagram
26
MSM85C154HVS Block Diagram
27
Timing and Control
28
Outline of MSM80C154S/MSM83C154S Timing
28
Major Synchronizing Signals
30
Ale
30
Psen
30
MSM80C154S Fundamental Operation Time Charts
31
External Program Memory Read Cycle Timing Chart
31
MOVX A, @Rr
31
MOVX @Rr, a
32
Movx A, @Dptr
32
MOV Direct, PORT[0, 1, 2, 3] Execution
33
Movx @Dptr, a
33
MSM83C154S Fundamental Operation Time Charts
34
MOVX @Rr, a
34
MOVX A, @Rr
34
Movx @Dptr, a
35
Movx A, @Dptr
35
MOV Direct, PORT[0, 1, 2, 3] Execution
36
Instruction Register (IR) and Instruction Decoder (PLA)
37
Arithmetic Operation Section
38
Outline
38
Arithmetic Operation Instruction Decoder
38
Arithmetic and Logic Unit (ALU)
38
Program Counter
39
Program Memory and External Data Memory
40
MSM80C154S/MSM83C154S Program Area and External ROM Connections
40
Procedures and Circuit Connections Used When External Data Memory (RAM) Is Accessed by Data Pointer (DPTR)
42
Procedures and Circuit Connections Used When External Data Memory (RAM) Is Accessed by Registers R0 and R1
45
3 Control
48
Oscillators [XTAL1 .2]
50
CPU Resetting
52
Outline
52
Reset Schmitt Trigger Circuit
57
CPU Internal Status by Reset
58
EA(CPU Memory Separate)
59
Outline
59
External ROM Mode
59
Internal ROM Mode
59
4 Internal Specifications
60
Internal Data Memory (RAM) and Special Function Registers
62
Outline
62
Internal Data Memory (RAM)
64
Internal Data Memory Registers R0 Thru R7
66
Stack
67
Internal Data Memory (RAM) Operating Procedures
68
Internal Data Memory Indirect Addressing
68
Internal Data Memory Register R0 Thru R7 Designation
69
Internal Data Memory 1-Bit Data Designation
70
Special Function Registers(TCON, SCON
72
Outline
72
Special Function Registers
74
Timer Mode Register (TMOD)
74
Power Control Register (PCON)
75
Timer Control Register (TCON)
76
Serial Port Control Register (SCON)
77
Interrupt Enable Register (IE)
78
Interrupt Priority Register (IP)
79
Program Status Word Register (PSW)
80
I/O Control Register (IOCON)
81
Timer 2 Control Register (T2CON)
82
Timer/Counters 0, 1, and 2
83
Outline
83
Timer/Counters 0 and 1
83
Timer/Counter 0 and 1 Counting Control
83
Timer/Counter 0 and 1 Count Clock Designation
85
External Clock Detector Circuit for Timer/Counters 0 and 1
86
Counting Control of Timer/Counters 0 and 1 by INT Pin
87
Mode 0
89
Outline
89
Timer/Counters 0/1 Timer Modes
89
Mode 1
91
Mode 2
93
Mode 3
95
32-Bit Timer Mode
96
Caution about Use of Timer Counters 0 and 1
97
Caution about Use of Timer Counters 0 and 1 When Setting Software Power down Mode
98
Timer/Counter 2
99
Outline
99
Timer 2 Control Register (T2CON)
99
Timer/Counter 2 Operation Modes
100
16-Bit Auto Reload Mode
100
16-Bit Capture Mode
101
16-Bit Baud Rate Generator Mode
102
Timer/Counter 2 Detector Circuit
104
T2(Timer/Counter 2 External Clock Detector)
104
T2Ex(Timer/Counter 2 External Flag Input Detector)
104
Timer/Counter Carry Signal Detector Circuit
105
Serial Port
106
Outline
106
Special Function Registers for Serial Port
108
Scon
108
Rclk
110
Sbuf
110
Tclk
110
Smod
111
Serr
112
Operating Modes
113
Mode 0
113
Mode 0 Baud Rate
113
Mode 0 Receive Operation
113
Mode 0 Transmit Operation
113
Outline
113
Mode 1
117
Mode 1 Baud Rate
117
Outline
117
Mode 1 Receive Operation
118
Mode 1 Transmit Operation
118
Mode 1 UART Error Detection
119
Mode 2
122
Mode 2 Baud Rate
122
Mode 2 Receive Operation
122
Mode 2 Transmit Operation
122
Outline
122
Mode 2 UART Error Detection
123
Mode 3
126
Mode 3 Baud Rate
126
Outline
126
Mode 3 Receive Operation
127
Mode 3 Transmit Operation
127
Mode 3 UART Error Detection
128
Serial Port Application Examples
131
I/O Extension
131
Multi-Processor Systems
135
Interrupt
136
Outline
136
Interrupt Enable Register (IE)
138
Interrupt Priority Register (IP)
139
Priority Interrupt Routine Flow
140
Interrupt Routine Flow When Priority Circuit Is Stopped
141
Interrupt Priority When Priority Register (IP) Contents Are All "0
142
Detection of External Interrupt Signals INT0 and INT1
143
External Interrupt Signal 0 and 1 Level Detection
143
Outline of INT Signal Detection
143
External Interrupt Signal 0 and 1 Trigger Detection
144
Interrupt Response Time Chart When Interrupt Conditions Are Satisfied During Execution of Ordinary Instruction in Main Routine
145
MSM80C154S/MSM83C154S Interrupt Response Time Charts
145
Interrupt Response Time Chart When Interrupt Conditions Are Satisfied During Execution of IE or IP Register Operation Instruction in Main Routine
147
Interrupt Response Time Chart When an Ordinary Instruction Is Executed after Temporarily Returning to the Main Routine from Continuous Interrupt Processing
149
Interrupt Response Time Chart When an IE or IP Manipulating Instruction Is Executed after Temporarily Returning to the Main Routine from Continuous Interrupt Processing
151
CPU "Power down
153
Idle Mode (IDLE) Setting
153
Outline
153
Caution about Software Power down Mode Setting
158
Soft Power down Mode (PD) Setting
158
Hard Power down Mode (HPD) Setting
168
CPU Power down Mode (IDLE, PD, and HPD) Cancellation (CPU Activation)
176
Cancellation by CPU Resetting (RESET Pin)
176
Outline
176
Cancellation of CPU Power down Mode (IDLE, PD) from Interrupt Address
183
Cancellation of CPU Power down Mode(IDLE, Pd)By Interrupt Signal
183
Cancellation of CPU Power down Mode (IDLE, PD) by Interrupt Request Signal and Restart from Next Address of Stop Address
189
MSM80C154S/83C154S Battery Backup with Hard Power down Mode
194
5 Input/Output Ports
197
Outline
199
Port 0
199
Port 1
202
Port 2
208
Port 3
210
Port 0, 1, 2, and 3 Output and Floating Status Settings in CPU Power down Mode (PD, HPD)
212
High Impedance Input Port Setting of each Quasi-Bidirectional Port 1, 2, and 3
214
Kw Pull-Up Resistance Setting for Quasi-Bidirectional Input Ports 1, 2, and 3
214
Precautions When Driving External Transistors by Quasi-Bidirectional
215
Port Output Signals
215
Port Output Timing
217
One Machine Cycle Instruction Output Timing
217
Two Machine Cycle Instruction Output Timing
218
Port Data Manipulating Instructions
219
6 Electrical Characteristics
221
Absolute Maximum Ratings
223
Operational Ranges
223
DC Characteristics
224
External Program Memory Access AC Characteristics
228
External Data Memory Access AC Characteristics
230
Serial Port (I/O Extension Mode) AC Characteristics
232
AC Characteristics Measuring Conditions
234
XTAL1 External Clock Input Waveform Conditions
235
7 Description of Instructions
236
Outline
238
Description of Instruction Symbols
239
List of Instructions
240
Simplified Description of Instructions
241
Detailed Description of MSM80C154S/MSM83C154S Instructions
253
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Oki MSM85C154HVS Specifications
General
Brand
Oki
Model
MSM85C154HVS
Category
Controller
Language
English
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