MSM80C154S/83C154S/85C154HVS
368
108. XRL A, Rr (Logical exclusive OR register to accumulator)
01101r2 r1 r0
70
Instruction code
Operation
Number of bytes
Number of cycles
Flags
(PSW)
Description
Example XRL A, R3
Instruction code
: Byte 1
(A)←(A) XOR (Rr) r=0 thru 7:
C AC F0 RS1 RS0 OV F1 P
•
:
:
:
The exclusive OR between the accumulator contents and the
register r contents is determined. The result is stored in the
accumulator and the flag is updated.
:
01101011
70
Byte 1
Accumulator
10100010
70
1
1
Before execution
Accumulator
10000111
70
After execution
:
Register 3
00100101
70
Register 3
00100101
70
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