LIST
OF
FIGURES
-
|
List
of
Figures
Figure
2.1
Maximum
input
voltage
versus
frequency.
...........cccccsccscesesesseeeeeesseees
2-3
FIGUG
71:
LOCK:
AGRE
cia
echccicearrns
cal
ausca
eee
tia
bear
tncedagsdetecce
ete
daoue
3-3
Figure
5.1
Adjusting
elements
on
vertical
PCD
oo...
cccccesessesesesecceseececsceccscseessens
5-3
Figure
5.2
Adjusting
elements
on
horizontal
pcb
0.0...
cceccesesececesceseseseevseseeseees
5-3
Figure
6.1
Dismantling
the
instruMent
..........ccccccccsesccecscscsssessssstseseevsvevssavececseesestaceasas
6-2
Figure
7.1
Removing
Vertical
pcb...
ecccssssssssescssssccsscsscscessecscescscesevassucarsscsscasceces
7-2
Figure
7.2
Removing
horizontal
pb..0........ccccccccccccscsesscsccceecseescessscsesessesaessssssesseecsess
7-3
Figure
7.3
Removing
Cal
and
Control
pCb........ccccccccssssscsesesessscsescssecesescsssvarecerecsesasace
7-3
PIQUIE-7.4
REMOVING
MOME:
POD
is
snictessdconscieveacdsciustatsiecueassinvinapesonsivelocdved
eatsauedanestaacts
7-4
Figure
7.5
Removing
text
plate
ccc
cceccscccsecscssecsssssscsceecsssecsssucsesecsesassevsesavescenees
7-5
PIQUHG
O51
FROUSIAG
sicisitecik
paste
siasipeve
So
asa
schesebhashctutualepace
Recvenastet
ected
adiatate
tsetse
deacstsedaanaec
9-3
PIQUIE
9:2:
FEOME
Payelcsui
cut
sccts
cout
sree
teoetavakcsnaieiasab
ati
nckyiagannscde
aoe
aaa
Releases
9-5
FIGUIC
9.3:
MANE
TREO
arises
cs
cbicsxgace
tales
cg
ocevisor
Weaiadtanost
aassdivdiadedaatelin
tod
eodnambeisacs
9-9
Figure.
1021
Vertical
pep
lay
OUbecciscsi
cre
cach
seartasdsseeceseens
yah,
Grovtehard
Weleda
Maecviness
10-3
Figure
10.2
Circuit
diagram
of
Vertical
input
........cc.cccccscscceessesessececeescsesesescsesesesees
10-5
Figure
10.3
Vertical
pcb
lay
Out...
ccc
ccscssssecesecsseseessccavscesescseaessssecscsscssesseseeeees
10-7
Figure
10.4
Circuit
diagram
of
vertical
amplifier
.........cccccccscsscsssesesecesestsccecsteesesees
10-9
Figure
10.5
Vertical
pcb
lay
Out...
ccc
cccsscecssssvscssecscsesevseteccssavseeaceucsecsesacseesseeeeeses
10-11
Figure
10.6
Circuit
diagram
of
vertical
output
amplifier
.......0.c.ccccccceeecsecseeseeeeees
10-13
Figure
10.7
Horizontal
pcb
lay
OUt..............cccssessssssssscsssssssssecestessecesscescasssstenecsceussune
10
-
15
Figure
10.8
Circuit
diagram
of
trigger
Generator
vo...
ceecsccecesescscecscescececescscsssececees
10-17
Figure
10.9
Horizontal
DCD
lay
OUP
sa
icesc
ces
esctsisscectes
eacieehedeeatiaas
denrancsn
Soacetveeccuelveacss
10-19
Figure
10.10
Circuit
diagram
of
main
time-base
generator
oo...
ccececcsessccescsesseeseees
10-24
Figure
10.11
Horizontal
BED
TEV
OUL
saeicer
teins
shits
testes
trcenatuald
angie
yates
See
ceeatl
tts
10-23
Figure
10.12
Circuit
diagram
of
horizontal
output
amplifier
.........ccccececccccscsceeeeees
10-2
Figure
10.13
Vertical
pcb
lay
out
showing
parts
of
power
SUDDIY
........
ce
eeeeeeeeeeees
10
-
27
Figure
10.14
Cal
and
control
pcb
lay
Out...
ccccscscseesecsssessescecetsssasescessveeseveees
10
-
2B
Figure
10.15
Circuit
diagram
of
power
supply
+
miscellane@OuS
.........cccccceccccceseees
10-9
Figure
10.16
Horizontal
pcb
lay
Out
........ccccccccsessssssssssssssssssecssecsssessossssssecsssesseecsesees
ve
10
-
Of
Fide
10517°CRT
pep
lay
Oty
5.c.uhs
5
wvcaceescakinss
nanehea
vine
vata,
a
coe
lcs
10-%@
Figure
10.18
Circuit
diagram
of
Z
-
amplifier
+
CRT
icccccccccccccsscsssseescececeseecesens
10
-
&
Figure
10.19
Mode
pcb
lay
Out
oo.
ee
eccccccccscsssescsesssscsesvscacscecarsessasscscsssssereseseseesseses
10-G