Philips TPM5.1E - Page 36

IC Data Sheets
EN 36 TPM5.1E LA8.
2011-Sep-02
8.3 Diagram B06 SSB Dali: DDR2 memory, NT5TU32M16CG-BD (IC U402, U403)
Figure 8-5 Internal block diagram and pin configuration
18291_300_090609.eps
100222
Block diagram
Pinning information
RAS
CAS
CK
CS
WE
CK
Control Logic
Column-Address
Counter/Latch
Mode
10
Command
Decode
A0-A12,
BA0, BA1
CKE
15
I/O Gating
DM Mask Logic
Bank0
Memory
Array
(8192 x 256 x 64)
Sense Amplifiers
Bank1
Bank2
Bank3
15
8
2
2
2
Refresh Counter
64
COL0
LDQ0-LDQ7
LDM
LDQS
Column
Decoder
256
(x64)
Row-Address MUX
Registers
13
16384
Bank0
Row-Address Latch
& Decoder
8192
Address Register
Bank Control Logic
15
Receivers
1
DQS
CK, CK
DLL
16
16
16
Input
Register
2
2
2
2
2
64
8
64
Data
Mask
Data
CK,
COL0,1
COL0,1
MUX
DQS
Generator
2
2
16
64
Read Latch
Write
FIFO
&
Drivers
Drivers
CK
16
16
DQS
2
2
16
16
16
16
16
16
16
16
LDQS
UDQS
UDQS
AP
13
UDQ0-UDQ7
UDM
Note: This Functional Block Diagram is intended to facilitate user understanding of the operation
of the device; it does not represent an actual circuit implementation.
Note: DM is a unidirectional signal (input only), but is internally loaded to match the load of the
bidirectional DQ and DQS signals.
A
B
C
D
E
F
G
H
J
K
L
× 16
1
VDD
DQ14
VDDQ
DQ12
VDD
DQ4
NC
VSSQ
DQ9
VSSQ
NC
VSSQ
DQ1
VSSQ
VREF
CKE
A10/AP
2
VSS
UDM
VDDQ
DQ11
VSS
LDM
VDDQ
DQ3
VSS
WE
BA1
3 7 8 9
A3
VDDQ
DQ15
VDDQ
DQ13
VDDQ
VDD
UDQS
VSSQ
DQ8
VSSQ
LDQS
VSSQ
DQ0
VSSQ
CK
CK
CS
VSSQ
UDQS
VDDQ
DQ10
VSSQ
LDQS
VDDQ
VSSDL
RAS
CAS
VDD
M
N
P
R
DQ6
VDDQ
VDDL
A7
A12VDD
BA0
A1
A5
A9
NC NC
A11
A6
A2
DQ2
NC
A8
A4
A0
DQ7
VDDQ
DQ5
VSS
NC
VSS
ODT