Quectel EG06 Series User Manual

LTE-A Module Series
EG06 Hardware Design
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PCM_CLK
PCM_SYNC
PCM_OUT
MSB
LSB
PCM_IN
125us
MSB
1 2 3231
LSB
Figure 24: Auxiliary Mode Timing
The following table shows the pin definition of PCM and I2C interfaces which can be applied on audio
codec design.
Table 15: Pin Definition of PCM and I2C Interfaces
Clock and mode can be configured by AT command, and the default configuration is master mode using
short frame synchronization format with 2048kHz PCM_CLK and 8kHz PCM_SYNC. Please refer to
document [1] for details about AT+QDAI command.
Pin Name
Pin No.
I/O
Description
Comment
PCM_IN
66
DI
PCM data input
1.8V power domain.
If unused, keep it open.
PCM_OUT
68
DO
PCM data output
1.8V power domain.
If unused, keep it open.
PCM_SYNC
65
IO
PCM data frame
synchronization
signal
1.8V power domain. In master mode, it
is an output signal. In slave mode, it is
an input signal.
If unused, keep it open.
PCM_CLK
67
IO
PCM data bit clock
1.8V power domain. In master mode, it
is an output signal. In slave mode, it is
an input signal.
If unused, keep it open.
I2C_SCL
43
OD
I2C serial clock
Require an external pull-up to 1.8V
I2C_SDA
42
OD
I2C serial data
Require an external pull-up to 1.8V

Quectel EG06 Series Specifications

General

Brand	Quectel
Model	EG06 Series
Category	Control Unit
Language	English