Quectel FGH100M - Page 17

Wi-Fi Module Series
FGH100M_Hardware_Design 17 / 41
SDIO_CMD
23
DIO
SDIO command
SDIO 2.0 compliant.
Reserve 10–100 kΩ
resistors to pull each of
them up to VDDIO.
SDIO_DATA0
25
DIO
SDIO data bit 0
SDIO_DATA1
26
DIO
SDIO data bit 1
SDIO_DATA2
19
DIO
SDIO data bit 2
SDIO_DATA3
20
DIO
SDIO data bit 3
JTAG Interface
Pin Name
Pin No.
I/O
Description
DC
Characteristics
Comment
JTAG_TDO
32
DO
JTAG test data out
VDDIO
Pull them down to GND
with 10 kΩ resistors.
JTAG_TMS
33
DI
JTAG test mode
select
JTAG_TDI
34
DI
JTAG test data in
JTAG_TCK
36
DI
JTAG test clock
JTAG_TRST
35
DI
JTAG test reset
GPIO Interfaces
Pin Name
Pin No.
I/O
Description
DC
Characteristics
Comment
GPIO0
10
DIO
General-purpose
input/output
VDDIO
Being multiplexed into
BUSY interface to indicate
Wi-Fi status. If needed,
please contact Quectel
Technical Support.
GPIO1
11
DIO
General-purpose
input/output
If unused, keep them open.
GPIO2
12
DIO
General-purpose
input/output
GPIO3
13
DIO
General-purpose
input/output
GPIO4
14
DIO
General-purpose
input/output
GPIO5
15
DIO
General-purpose
input/output