Quectel LPWA Series Hardware Design

LPWA Module Series
BG950A-GL&BG951A-GL_Hardware_Design
45
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AT+IPR* can be used to set the baud rate of the main UART interface, and AT+IFC* can be used to set
the hardware flow control (the function is disabled by default). See document [3] for more details about
these AT commands.
Table 18: Pin Definition of Debug UART Interface
Table 19: Pin Definition of Auxiliary UART Interface
The module provides 1.8 V UART interfaces. A voltage-level translator should be used if the application
is equipped with a 3.3 V UART interface. The following figure shows a reference design of the main
UART interface:
Figure 18: Reference Circuit with Translator Chip
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Pin Name
Pin No.
I/O
Description
Comment
DBG_TXD
23
DO
Debug UART transmit
1.8 V power domain
If unused, keep this pin open.
DBG_RXD
22
DI
Debug UART receive
Pin Name
Pin No.
I/O
Description
Comment
AUX/GNSS_TXD
27
DO
Auxiliary/GNSS UART transmit
1.8 V power domain
If unused, keep this pin open.
AUX/GNSS_RXD
28
DI
Auxiliary/GNSS UART receive
NOTE

Quectel LPWA Series Specifications

General

Brand	Quectel
Model	LPWA Series
Category	GSM/GPRS Modules
Language	English