Quectel LTE Standard Module Series User Manual

LTE Module Series
EG21-G Hardware Design
EG21-G_Hardware_Design 46 / 100
PCM_SYNC
26
IO
PCM data frame
synchronization signal
1.8V power domain
PCM_CLK
27
IO
PCM data bit clock
1.8V power domain
I2C_SCL
41
OD
I2C serial clock
Require external pull-up to 1.8V
I2C_SDA
42
OD
I2C serial data
Require external pull-up to 1.8V
Clock and mode can be configured by AT command, and the default configuration is master mode using
short frame synchronization format with 2048KHz PCM_CLK and 8KHz PCM_SYNC. Please refer to
document [2] for more details about AT+QDAI command.
The following figure shows a reference design of PCM interface with external codec IC.
PCM_IN
PCM_OUT
PCM_SYNC
PCM_CLK
I2C_SCL
I2C_SDA
Module
1.8V
4.7K 4.7K
BCLK
LRCK
DAC
ADC
SCL
SDA
BIAS
MICBIAS
INP
INN
LOUTP
LOUTN
Codec
Figure 24: Reference Circuit of PCM Application with Audio Codec
1. It is recommended to reserve an RC (R=22Ω, C=22pF) circuits on the PCM lines, especially for
PCM_CLK.
2. EG21-G works as a master device pertaining to I2C interface.
3.13. SD Card Interface
EG21-G supports SDIO 3.0 interface for SD card.
The following table shows the pin definition of SD card interface.
NOTES

Quectel LTE Standard Module Series Specifications

General

Brand	Quectel
Model	LTE Standard Module Series
Category	Wireless modules
Language	English