Quectel LTE Standard Module Series User Manual

LTE Module Series
EG21-G Hardware Design
EG21-G_Hardware_Design 22 / 100
analog to digital
converter
0.3V to VBAT_BB
open.
ADC1
44
AI
General purpose
analog to digital
converter
Voltage range:
0.3V to VBAT_BB
If unused, keep it
open.
PCM Interface
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
PCM_IN
24
DI
PCM data input
V
IL
min=-0.3V
V
IL
max=0.6V
V
IH
min=1.2V
V
IH
max=2.0V
1.8V power domain.
If unused, keep it
open.
PCM_OUT
25
DO
PCM data output
V
OL
max=0.45V
V
OH
min=1.35V
PCM_SYNC
26
IO
PCM data frame
synchronization
signal
V
OL
max=0.45V
V
OH
min=1.35V
V
IL
min=-0.3V
V
IL
max=0.6V
V
IH
min=1.2V
V
IH
max=2.0V
1.8V power domain.
In master mode, it is
an output signal. In
slave mode, it is an
input signal.
If unused, keep it
open.
PCM_CLK
27
IO
PCM clock
V
OL
max=0.45V
V
OH
min=1.35V
V
IL
min=-0.3V
V
IL
max=0.6V
V
IH
min=1.2V
V
IH
max=2.0V
I2C Interface
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
I2C_SCL
41
OD
I2C serial clock.
Used for external
codec.
An external pull-up
resistor is required.
1.8V only. If unused,
keep it open.
I2C_SDA
42
OD
I2C serial data.
Used for external
codec.
An external pull-up
resistor is required.
1.8V only. If unused,
keep it open.
SD Card Interface
Pin Name
Pin No.
I/O
Description
DC Characteristics
Comment
SDC2_
DATA3
28
IO
SD card SDIO bus
DATA3
1.8V signaling:
V
OL
max=0.45V
SDIO signal level can
be selected

Quectel LTE Standard Module Series Specifications

General

Brand	Quectel
Model	LTE Standard Module Series
Category	Wireless modules
Language	English