4. AVDD, AF_VDD, DVDD, and DOVDD must be provided by the terminal board. If the camera has
power supply timing requirements, the timing control can be performed through the module’s GPIO.
5. The power domain of CAM1_MCLK is 3.3 V. If it does not match with the camera’s power domain, the
level-shift is required.
4.11.1. MIPI Design Considerations
To ensure performance, the following principles should be complied with when designing LCM and
camera interfaces:
⚫ Special attention should be paid to the pin description of LCM and camera interfaces. Different video
devices will have varied definitions for their corresponding connectors. Ensure that the devices and
the connectors are correctly connected.
⚫ MIPI are high-speed signal traces, supporting maximum data rate up to 2.5 Gbps. The differential
impedance should be controlled to 100 Ω. Additionally, it is recommended to route the traces on the
inner layer of PCB and do not cross it with other traces. For the same video device, keep all the MIPI
traces be of the same length. To avoid crosstalk, a clearance of 3 times the trace width is
recommended among MIPI signal traces. During impedance matching, do not connect MIPI signal
traces to GND on different planes to ensure impedance consistency.
⚫ It is recommended to select a TVS of low capacitance for ESD protection and the recommended
parasitic capacitance should be lower than 1 pF.
⚫ Route MIPI traces according to the following requirements:
a) The total trace length should not exceed 150 mm;
b) Control the differential impedance to 100 Ω ±10 %;
c) Control intra-lane length matching within 0.3 mm;
d) Control inter-lane length matching within 0.9 mm.
Table 28: MIPI Trace Length Inside the Module (Unit: mm)
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