User’s Manual 95
8.3.2 MMU Instruction/Data Register
8.3.2.1 Instruction and Data Space Support
Support for Instruction and Data space (I and D space) support was added in revisions A–C
by optionally inverting address lines A16 and/or A19 when the processor accesses D
space, but not inverting those lines when the processor accesses I space. The MMIDR reg-
ister is used to control this inversion. Refer to Section B.2.5 for more information on using
I and D space on the Rabbit 2000 chip. More information on separate I and D implementa-
tion will be available in the Rabbit 2000 Designer’s Handbook, and is currently available
in the Rabbit 3000 Designers Handbook.
8.3.2.2 /CS1 Enable
The optional enable of /CS1 is valuable for systems that are pushing the access time of
battery-backed RAM. By enabling /CS1, the delay time of the switch that forces /CS1
high when power is off can be bypassed. This feature increases power consumption since
the RAM is always enabled and its access is controlled normally by /OE1. This option is
enabled by setting bit 4 in the MMIDR register. See Section B.2.5 for more information.
8.3.3 Memory Timing Control Register
8.3.3.1 Early Memory Output-Enable Feature
The early I/O enable feature was added to the Rabbit 2000C revision to relax the tight tim-
ing requirements for memory access when using the clock spectrum spreader. See
Section B.2.13 for more information.
To Next Page
Loading...
