74 Rabbit 2000 Microprocessor
7.3 Clock Doubler
The clock doubler is provided to allow a lower frequency crystal to be used for the main
oscillator and to provide an added range of clock frequency adjustability. The clock dou-
bler is controlled via the Global Clock Double Register as shown in Table 7-2.
Table 7-3 lists the recommended values or “settings” for the Global Clock Double Register
for various oscillator frequencies.
Table 7-2. Global Clock Double Register (GCDR, adr = 0x0F)
Bit(s) Value Description
7:3 xxxxx These bits are ignored.
2:0 000 The clock double circuit is disabled.
001 8 ns nominal low time.
010 10 ns nominal low time.
011 12 ns nominal low time.
100 14 ns nominal low time.
101 16 ns nominal low time.
110 18 ns nominal low time.
111 20 ns nominal low time.
Table 7-3. Recommended Delays Set In GCDR for Clock Doubler
Recommended GCDR Value Frequency Range
7 ≤11.0592 MHz
6 11.0592–12.9024 MHz
5 12.9024–14.7576 MHz
4 14.7576–16.5888 MHz
3 16.5888–20.2752 MHz
2 20.2752–23.9616 MHz
1 23.9616–31.3344 MHz
0 >31.3344 MHz
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