138 Rabbit 2000 Microprocessor
The slave port has three data registers for each direction of communication. Three regis-
ters, SPD0R, SPD1R, and SPD2R, can be written by the master and read by the slave.
Three different registers, also named SPD0R, SPD1R, and SPD2R, can be written by the
slave and read by the master. The same names are used for different registers since it is
usually clear from the context which register is meant. If it is necessary to distinguish
between registers, we will refer to the registers as “SPD0R writable by the slave” or
“SPD0R writable by the master.”
A status register can be read by either the slave or the master. The status register has full/
empty bits for each of the six registers. A data register is considered full when it is written
to by whichever side is capable of writing to it. If the same register is then read by either
side it is considered to be empty. The flag for that register is thus set to a "1" when the reg-
ister is written to, and the flag is set to a "0" when the register is read.
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