Rabbit 2000 - Page 4

Rabbit 2000 Microprocessor
Chapter 4. Rabbit Capabilities 41
4.1 Precisely Timed Output Pulses .......................................................................................................... 41
4.1.1 Pulse Width Modulation to Reduce Relay Power .....................................................................43
4.2 Open-Drain Outputs Used for Key Scan............................................................................................ 44
4.3 Cold Boot ........................................................................................................................................... 45
4.4 The Slave Port.................................................................................................................................... 46
4.4.1 Slave Rabbit As A Protocol UART ...........................................................................................47
Chapter 5. Pin Assignments and Functions 49
5.1 Package Schematic and Pinout...........................................................................................................49
5.2 Package Mechanical Dimensions....................................................................................................... 50
5.3 Rabbit Pin Descriptions......................................................................................................................52
5.4 Bus Timing.........................................................................................................................................58
5.5 Description of Pins with Alternate Functions ....................................................................................59
5.6 DC Characteristics.............................................................................................................................. 61
5.6.1 5.0 Volts ....................................................................................................................................62
5.6.2 3.3 Volts ....................................................................................................................................63
5.7 I/O Buffer Sourcing and Sinking Limit.............................................................................................. 64
Chapter 6. Rabbit Internal I/O Registers 65
6.1 Default Values for all the Peripheral Control Registers.....................................................................65
Chapter 7. Miscellaneous I/O Functions 71
7.1 Processor Identification......................................................................................................................71
7.2 Rabbit Oscillators and Clocks............................................................................................................ 72
7.3 Clock Doubler.................................................................................................................................... 74
7.4 Controlling Power Consumption........................................................................................................ 76
7.5 Output Pins CLK, STATUS, /WDTOUT, /BUFEN.......................................................................... 77
7.6 Time/Date Clock (Real-Time Clock).................................................................................................78
7.7 Watchdog Timer.................................................................................................................................80
7.8 System Reset...................................................................................................................................... 82
7.9 Rabbit Interrupt Structure................................................................................................................... 84
7.9.1 External Interrupts .....................................................................................................................86
7.9.2 Interrupt Vectors: INT0 - EIR,0x00/INT1 - EIR,0x08 ..............................................................87
7.10 Bootstrap Operation ......................................................................................................................... 88
Chapter 8. Memory Mapping and Interface 91
8.1 Memory-Mapping Unit ...................................................................................................................... 91
8.2 Memory Interface Unit.......................................................................................................................93
8.3 Memory Control Unit Registers.........................................................................................................94
8.3.1 Memory Bank Control Registers ...............................................................................................94
8.3.2 MMU Instruction/Data Register ................................................................................................ 95
8.3.3 Memory Timing Control Register .............................................................................................95
8.4 Allocation of Extended Code and Data..............................................................................................96
8.5 How Compiler Compiles to Memory................................................................................................. 97
Chapter 9. Parallel Ports 99
9.1 Parallel Port A..................................................................................................................................100
9.2 Parallel Port B ..................................................................................................................................101
9.3 Parallel Port C ..................................................................................................................................102
9.4 Parallel Port D..................................................................................................................................103
9.5 Parallel Port E................................................................................................................................... 106
Chapter 10. I/O Bank Control Registers 109