Radio Shack CCR-81 Technical Manual

Z8
is the
graphics
generator. Actually,
Z8
does
not generate
anything. Rather,
it
steers the ASCII
addresses
around to
simulate
a
graphics generator.
The
input
to
Z8
is ASCII
from data
latch Z28,
and the
higher
order line
address from
Z12,
L4 and L8. L4
and L8 can
represent
any
four numbers
from
to
3.
But since Z12
never
goes
to
binary
12 (except
for
so short
a time we
can ignore
it),
we will
only be
looking for
a binary
number
from
to 3. L8
and L4
are
used
to specify the
vertical
address
of the
six graphic cells.
There
are three vertical
addresses:
00
defines
the uppermost
pair
of cells,
01
defines the
middle
pair of
cells, 10 defines
the lower
pair. This is
also shown
in Figure
3.
The ASCII
word, labeled
LB0
through
LB5,
determines
if
the
graphics cell
is
ON
(high)
or
OFF
(low).
The position
of
one of these inputs
to Z8
determines
which
side of the
center line
the cell
is located.
An input
at pin
6 of
Z8
specifies
a
left
hand graphic
cell.
Input
at pin
10
of Z8
specifies
a
right
hand
graphics cell. Pin
5,
left;
pin
11,
right;
pin
4,
left; pin
12,
right. For
example:
Assume LB2
is
high
and all other
LB inputs
to
Z8
are low. LB2
comes into Z8
at
pin 5.
This
pin is
associated
with
a graphic cell
location
on
the
left
of the character
position.
Therefore,
depending
on the status
of
L8
and L4,
LB2
will turn
on (light)
one of
the
graphic cells
on the left
of center line.
If L3
and L4 are
at logical
00,
the upper
left cell
is turned
on. If L3
and
L4
are
01,
the middle left
cell will
light.
As you can
see,
Z8's
function
as a graphics
generator
is to
steer the ASCII
bits
around the
character
rectangle. The
vertical position
of the
graphics
in the cell
is determined
by
the status
of L8 and L4.
The
two outputs
from Z8
are
labeled
"left" and
"right". This
"dot"
information
is
applied to the
graphics shift
register. It
is in
shift register
logic that
data from RAM
Z63
determines
if graphics
or
alphanumerics
will be
written
in
any one
character
rectangle.
ALPHANUMERIC/GRAPHIC
SHIFT
REGISTER
Z10
is the alphanumeric
shift
register
and Z11
is the
graphic
register. Both
devices
receive
parallel
data from
their
respective generators. The
parallel
dot data is loaded
into
the registers and
the dot clock
(labeled SHIFT)
will
march
the dots out,
one behind
the other,
to
the
video
Mixer.
We will discuss
the alphanumeric
shift register
first.
There
are
a few restrictions
when
the alphanumeric
shift
register
may serialize
dot data and
when
it shouldn't.
First,
the
data must be
alphanumeric
and
not graphic.
Second,
the electron
beam must be
on one
of the
seven scan lines
that
are reserved for
dot data
and not
on one of
the five
lines
that are blanked
(held
off) between
character
lines.
Third,
the electron
beam must
be on
one of the
192 scan
lines
that define
the video
portion of
the screen,
(not in
boundary
space
-
upper, lower,
left
or right).
Once all
three
restrictions are met,
the dot
data is
parallel loaded
into the
register. NAND
gate Z26
insures
all conditions
are
met
before
data is stored in Z10.
Delay
bit
7*
is sourced
from latch Z27,
pin
2,
and applied
to pin
10
of Z26.
When this
input is
high, data in Z63
is
low,
which
defines
an alphanumeric
character.
Delay
L8 is sourced
at Z27,
pin
11,
and is connected
to
Z26,
pin
12. When this input
is high,
the beam
is scanning
in
a character
line and not
between
character lines.
Delay
BLANK
is sourced
at pin 7
of
latch
Z27
and is tied
to pin
9
of
Z26.
When this input
is high,
the electron
beam
is
in the video
portion
of the screen
and is
not located
near
a sync pulse
or in some
boundary
region.
All
three
restrictions
have then been
met. Pin
13
of
Z26
is
tied
to the inverted
signal, LATCH.
When
pin 13
of Z26
goes high,
the dot load
process will be
activated
by
a
low
on Z26,
pin
8.
Upon
the next clock
pulse
at pin 7
of
Z10,
dot
data will be loaded
into the
shift register.
After LATCH
goes back high
(one dot time
after
going low),
the shift
register
starts clocking dot
data out
at pin 13
in a serial
stream
(when LATCH
goes high,
pin 13 of Z26
goes
low
causing
pin
8 to go
high). Each
time LATCH
goes
high,
it
forces
ASCII
and conditional
data
to be stored
in
Z27
and
Z28. During
this
time, Z10 will
not be
shifting
dots out
at pin
13.
Z10
only
shifts data
out when
pin 15 is
high.
When low,
pin 15 forces Z10
to load
data from
the charac-
ter generator.
Notice
the unused
inputs
to
Z10.
Pin
9,
the clear
input,
is pulled
up, via R40,
to
VqC-
When
this pin
is low (due
to
a short), you
would have
a blank screen.
Pins
14,
3, 2,
1
and
6
are tied
to ground.
Pin
14 gives
you that blank
dot
between
adjacent characters.
Pins
2 and 3 are
not used, but
are register
inputs like
pin 4
or 5.
Pin
1 is
for serial
data
input
and pin
6 inhibits the
clock input.
They
are not nec-
essary in
this application.
The
graphics shift
register is Z11.
Operation is
almost the
same
as
Z10,
except
for the condition
that must
be met for
use. The
graphics conditions
are
as
follows:
First, Z63
must
specify
a graphics character
instead
of an alphanumeric
character.
Second,
the electron
beam must be in
the video
region
of
the screen. There
are only
two conditions
restrict-
ing
graphics. Since
a
character
rectangle
ends
where another
starts,
there is no
inter-character line
blanking. If
you turn
on all
of the
graphic cells, you
would have
a full, large
square with
no holes and
boundaries
surrounding
the
square. Once
all of the restrictions
are met,
graphic
dot data
may be loaded
into Z1
1
for
shifting
to the video
mixer. The
other NAND
gate
in Z26
is used
as the graphics
load enable.
The
inverse of delay
bit
7*
(DLY
bit
7)
is sourced
at Z27,
pin
3.
It
is applied
to
Z26,
pin 4. When
high, this
input tells
Z26
that Z63
does indeed
contain
a
"1"
which
defines
a
graphic code.
19

Radio Shack CCR-81 Specifications

General

Brand	Radio Shack
Model	CCR-81
Category	Desktop
Language	English