Rigol DS1074Z Plus User Manual

RIGOL Chapter 8 Protocol Decoding
8-2 MSO1000Z/DS1000Z User’s Guide
Parallel Decoding
Parallel bus consists of clock line and data line. As shown in the figure below, CLK is
the clock line, while Bit0 and Bit1 are the 0 bit and 1st bit on the data line respectively.
The oscilloscope will sample the channel data on the rising edge, falling edge or the
rising/falling edge of the clock and judge each data point (logic "1" or logic "0")
according to the preset threshold level.
Figure 8-1 Parallel Decoding
Press MATH  Decode1  Decoder to select "Parallel" and open the parallel
decoding function menu.
1. Press Decode to turn on or off the decoding function.
2. Clock Line Setting (CLK)
 Press CLK to select any channel (CH1-CH4 or D0-D15) as the clock channel.
If "OFF" is selected, no clock channel is set.
 Press Edge to set the oscilloscope to sample the channel data on the rising
edge (
), falling edge ( ) or rising/falling edge ( ) of the clock. If
no clock channel is selected, the instrument will sample when the channel
data jumps during the decoding.
3. Digital Bus
Press BUS to select the digital bus for parallel decoding. This setting will
automatically modify the settings of Width, Bit X and CH, as shown in the table
on the next page.
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Rigol DS1074Z Plus Specifications

General

Type	Tabletop
Product type	-
Certification	UL 61010-1:2004; CAN/CSA-C22.2 NO. 61010-1-2004; EN 61010-1:2001; IEC 61010-1:2001
Bandwidth	70 MHz
Sampling rate	- MS/s
Channels quantity	4 channels
Minimum time base setting (per division)	5 ns
Power consumption (max)	50 W
Display diagonal	7 \
Non-operating altitude	3000 - 15000 m
Storage temperature (T-T)	-40 - 70 °C
Operating temperature (T-T)	0 - 50 °C

Weight and Dimensions

Depth	122.4 mm
Width	313.1 mm
Height	160.8 mm