RK3288 Hardware Design Guide
DDRIO_RETLE is the input pin of enabled signal for DDR controller retention latch.
DDR PHY can run into self-refresh module to reduce the power consumption, and the
voltage level of the DDR_RETLE should be keep the same with VCC_DDR. Match the
voltage level by two divider resistors R1204 (120K) and R1206 (120K) for DDR3 mode,
as shown in Fig 8-4. Please adjust the value of R1204 (100K) and R1206 (82K) for
LPDDR2/3 mode.
Fig 8-4
The divider resistor value of reference power supply should be sure 1% accuracy.
While in deep sheep, VREF_DDR0 can be turned off, but not for VREFAO_DDR0. So
10K divider resistors is used to reduce the power consumption. In order to keep the
following performance of power, resistors should be connected in parallel with 0.1uF
capacitor, as shown in Fig 8-5:
Fig 8-5
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