Sanyo DC-F320 - IC104 CXD2508 AQ (Digital Signal Processor); IC361 BU2090 F

IC BLOCK DIAGRAM & DESCRIPTION
IC104 CXD2508AQ (DIGITAL SIGNAL PROCESSOR)
15
DATO
16
XLTO
17
CLKO
0 Outputs serial data to SSP.
o Outputs latches tc SSP. Serial data latches at
falling edge.
I Outputs sertal data transfer clock to SSP.
succession.
28
TEST
I Pin for TEST. Normal used stage : GND.
23
FILO
o 0%“’ c4 filter for master PLL. (Slave = Digital
30
31
32
33
34
36
L
36
37
38
33
40
l-U_,
FILI
I Inputs to filter for master PLL.
PC0
0 Outputs of charge pump for master PLL.
VDD
- Power supply for digital. (+5V)
AVSSI
- Power supply for analog. (OV)
CLTV
I VC0 control voltage input for master PLL.
AVDDl -
Power supply for analog. (+5V)
RF
BIAS
ASYI
ASYO
EFM fill swina output. (IL] = VSS, [HI = VDD)
ASYE
I [L] : OFF of asymmetty correction. [H] : ON c4
I
asymmetly correction.
IC361 BU209OF
DATA
CLOCK
vss
VDD
I
F,
*
+
OUTPUT BUFFER (OPEN DLAIN)
- 30 -
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