Sanyo PLC-XF71 - Page 151

-151-
IC Block Diagrams
BRIDGE
BUS STATE
CONTROLLER
(BSC)
MEMORY
MANAGEMENT
UNIT
(MMU)
CPU BUS
(L BUS.... I_CLOCK)
CASH
MEMORY
DSP CORE
Super H
CPU CORE
SRAM
(XY RAM)
CPU/DSP DATA
CASH ACCESS
CONTOROLLER
(CCN)
USER
BRAKE
CONTROLLER
(UBC)
DIRECT MEMORY
ACCESS
CONTOROLLER
(DMAC)
INTERNAL
OSCILLATION
CIRCUIT
( CPG)
USER DEBUG
INTERFACE
(H-UDI)
INTERACTIVE
CONTOROLLER
(INTC)
INTERNAL BUS(I_CLOCK)
INTERNAL BUS2 (I2_CLOCK)
D/A
CONVERTER
(DAC)
A/D
CONVERTER
(ADC)
SERIAL
COMMUNICATION
INTERFACE
(SCIF)
PERIPHERAL BUS
CONTOROLLER
TIMER
(TMU)
SERIAL
SMART CARD
(SCI)
REAL TIME
CLOCK
(RTC)
PERIPHERAL BUS1 (P1_CLOCK)
PERIPHERAL BUS (P_CLOCK)
PERIPHERAL BUS2 (P2_CLOCK)
512byte
SRAM
128byte
SRAM
288byte
SRAM
ANALOG
FRONT END
INTERFACE
(AFEIF)
AUDIO
CODEC
INTERFACE
(SIOF)
PC CARD
CONTROLLER
(PCC)
USB
FUNCTION
CONTROLLER
(USBF)
LI BUS STATE
CONTROLLER
(LBSC)
ARBITRATION
LI BUS (B_CLOCK)
2.4K byte
LINE BUFFER
SRAM
512 byte
PALLET
SRAM
LCD CONTROLLER
(LCDC)
USB HOST CONTROLLER
(USBH)
● HD6417727F <CPU[SH3], IC801>