39
LC-32LE240
LC-40LE240
8. DDR2 SDRAM K4T1G164QF (U155)
Description:
The 1Gb DDR2 SDRAM is organized as a 16Mbit x 8 I/Os x 8 banks, 8Mbit x 16 I/Os x 8
banks device. This synchronous device achieves high speed double-data-rate transfer
rates of up to 1066Mb/sec/pin (DDR2-1066) for general applications. The chip is designed
to comply with the following key DDR2 SDRAM fea-tures such as posted CAS with
additive latency, write latency = read latency - 1, Off-Chip Driver(OCD) impedance
adjustment and On Die Termination. All of the control and address inputs are
synchronized with a pair of exter-nally supplied differential clocks. Inputs are latched at
the crosspoint of dif-ferential clocks (CK rising and CK falling). All I/Os are synchronized
with a pair of bidirectional strobes (DQS and DQS) in a source synchronous fash-ion. The
address bus is used to convey row, column, and bank address information in a RAS/CAS
multiplexing style. For example, 1Gb(x8) device receive 14/10/3 addressing. The 1Gb
DDR2 device operates with a single 1.8V ± 0.1V power supply and 1.8V ± 0.1V VDDQ.
The 1Gb DDR2 device is available in 60ball FBGA(x8) and 84ball FBGA(x16).
Features:
• JEDEC standard VDD = 1.8V ± 0.1V Power Supply
• VDDQ = 1.8V ± 0.1V
• 533MHz fCK for 1066Mb/sec/pin
• 8 Banks
• Posted CAS
• Programmable CAS Latency: 4, 5, 6, 7
• Programmable Additive Latency: 3, 4, 5. 6
• Write Latency(WL) = Read Latency(RL) -1
• Burst Length: 4 , 8(Interleave/nibble sequential)
• Programmable Sequential / Interleave Burst Mode
• Bi-directional Differential Data-Strobe (Single-ended data-strobe is an optional feature)
• Off-Chip Driver(OCD) Impedance Adjustment
• On Die Termination
• Special Function Support - PASR(Partial Array Self Refresh) - 50ohm ODT - High
Temperature Self-Refresh rate enable
• Average Refresh Period 7.8us at lower than TCASE 85°C, 3.9us at 85°C < TCASE < 95
°C
• All of products are Lead-free, Halogen-free, and RoHS compliant
8.2 Features
8.1 General Description
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