104
lc
P/
Instruction z v s
N
H Comments
ADD
A,
s; ADC
A,
s
t
v
0
t
8-bit add or add with carry
SUB
s;
SBC
A,
s;
CP
s; NEG
t
v
t
t
8-
bit
subtract, subtract with carry, compare and negate accumulator
AND s
0
p
t
0 1
} Logical operations
OR
s;
XOR s
0
t
p
0 0
And set's different flags
INC s
•
v
t
0
t
8-bit increment
DECm
•
t
v
t
1 8-bit decrement
ADD DD,
ss
• • •
0
X 16-bit add
ADC HL,
ss
t
v
0
X 16-bit add with
ca
rry
SBC
HL,
ss
t
v X
16-bit subtract with carry
RLA;
RLCA;RRA;RRCA;
•
• •
0 0
Rotate accumulator
RL m;
RLC m;
RR
m; RRC m
t
p
0 0
Rotate
and shift location s
SLAm;
SRA m; SRL m
RLD;RRD
•
t
p
0 0
Rotate
digit left and right
DAA
t
p
t
•
Decimal adjust accumulator
CPL
•
•
• •
1 Complement accumulator
SCF
1
•
• •
0 0
Set
carry
CCF
t
• •
•
0
X
Complement carry
IN r,
(C)
•
p
0 0
Input
register indirect
INI; IND;
OUTI; OUTD
•
X X
X
} Block input and
output
INIR; INDR; OTIR; OTDR
•
X
X X
Z = 0
if
B
1'
0 otherwise Z = 1
LDI; LDD
•
X
t
X
0
0
} Block transfer instructions
LDIR;LDDR
•
X
0
X
0 0 P/V = 1
if
BC
1'
0, otherwise P/V = 0
CPI; CPIR; CPD; CPDR
•
t
X
X Block search instructions
Z = 1
if
A = (HL), otherwise Z = 0
P/V
= 1 if
BC
1'
0, otherwise P/V = 0
LD
A, I;
LD
A,
R
•
FF
t
0 0
The
content
of
the interrupt enable flip-flop (IFF)
is
copied
into
the
P/V
flag
BIT b, s
•
X X
0
1 The state
of
bit
b
of
location s
is
copied
into
the Z flag
NEG
v
t t
Negative accumulator
The following
not
ation
is
used in this table:
Symbol Operation
C Carry/link flag. C = 1
if
the operation produced a carry from the
MSB
of
the
operand or result.
Z Zero flag. Z = I
if
the result
of
the operation
is
zero.
S Sign flag. S = I
if
the
MSB
of
the result
is
one.
P/V Parity or overflow flag. Parity (P) and overflow (V) share the same flag. Logical operations affect this flag with the parity
of
the result while arithmetic operations affect this flag with the overflow
of
the result.
If
P/V holds parity, P/V = 1
if
the
result
of
the operation
is
even, P/V = 0 if result
is
odd.
If
P/V holds overflow, P/V = I
if
the result
of
the
operation produced
an overflow.
H Half-carry flag. H
= I if the add or subtract operati
on
produced a carry into or borrow from into bit 4
of
the accumulator.
N Add/Subtract flag. N
= 1
if
the previous operation was a subtract.
H and N flags are used in conjunction with the decimal adjust instruction (DAA)
to
properly correct
the
result into packed
BCD
format following additi
on
or subtraction using operands with packed
BCD
format.
The flag
is
affected according
to
the result
of
the operation.
• The flag
is
unchanged by the operation.
0 The flag
is
reset by the operation.
I The flag
is
set by the operation.
X The flag
is
a
"don't
care."
V P
/V
flag
affected according to the overflow result
of
the operation.
P P /V flag affected according to the parity result
of
the operation.
Any one
of
the
CPU
registers
A,
B, C,
D,
E,
H,
L.
Any 8-bit location for all the addressing modes a
ll
owed for the particular instruction.
ss
Any 16-bit location for all the addressing modes allowed for that instruction.
ii Any
one
of
the two index registers IX or IY.
R Refresh counter.
n 8-bit value in range
<0, 255>
nn I6-bit value in range
< 0, 65535>
m Any 8-bit location for all the addressing modes allowed for the particular instruction.
SUMMARY
OF
FLAG
OPERATION
TABLE
4.4
-1
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