105
5.0
INTERRUPT
RESPONSE
The purpose
of
an interrupt
is
to allow peripheral devices
to
suspend CPU operation in an orderly manner and
force the
CPU to start a peripheral service routine. Usually this service routine
is
involved with the exchange
of
data, or
status and control information, between the
CPU and the peripheral. Once the service routine
is
completed, the CPU
returns
to
the operation from which it was interrupted.
INTERRUPT
ENABLE-
DISABLE
The Z-80A CPU has two interrupt inputs, a software maskable interrupt and a non maskable interrupt. The non
maskable interrupt (NMI) can
not
be disabled by the programmer and it will be accepted whenever a peripheral device
requests it. This interrupt
is
generally reserved for very important functions that must be serviced whenever they occur,
such as an impending power failure. The maskable interrupt (INT) can be selectively enable or disabled
by
the program-
mer. This allows the programmer
to
disable the interrupt during periods where his program has timing constraints
that
do
not
allow it
to
be interrupted. In the Z-80A CPU there
is
an enable flip flop (called
IFF)
that
is
set or reset
by
the
programmer using the Enable Interrupt (EI) and Disable Interrupt (Dl) instructions. When the
IFF
is
reset, an interrupt
can
not
be accepted
by
the CPU.
Actually, for purposes
that
will be subsequently explained, there are two enable flip flops, called
IFF
1
and
IFF
2
.
Actually disables interrupts
from being accepted.
Temporary storage location
for
IFF
1
•
The state
of
IFF
1
is
used to actually inhibit interrupts while
IFF
2
is
used
as
a temporary storage location for
IFF
1
.
The purpose
of
storing the
IFF
1
will be subsequently explained.
A reset
to
the CPU will force
both
IFF
1
and
IFF
2
to
the reset state so
that
interrupts are disabled. They can then
be enabled
by
an EI instruction
at
any time
by
the programmer. When an EI instruction
is
executed, any pending inter-
rupt request will
not
be accepted until after the instruction following EI has been executed. This single instruction
delay
is
necessary for cases when the following instruction
is
a return instruction and interrupts must not
be
allowed
until the return has been completed. The EI instruction sets
both
IFF
1
and
IFF
2
to
the enable state. When an interrupt
is
accepted
by
the CPU,
both
IFF
1
and
IFF
2
are automatically reset, inhibiting further interrupts until the programmer
wishes to issue a new EI instruction. Note
that
for all
of
the previous cases,
IFF
1
and
IFF
2
are always equal.
The purpose
of
IFF
2
is
to
save
the status
of
IFF
1
when a
non-
maskable interrupt occurs. When a non maskable
interrupt
is
accepted,
IFF
1
is
reset to prevent further interrupts until reenabled
by
the programmer. Thus, after a non
maskable interrupt has been accepted, maskable interrupts are disabled
but
the previous state
of
IFF
1
has been saved
so
that
the complete state
of
the
CPU
just prior to the non maskable interrupt can be restored
at
any time. When a Load
Register A with Register I (LD A, I) instruction or a Load Register A with Register R (LD A,
R)
instruction
is
exe-
cuted, the state
ofiFF
2
is
copied into the parity flag where it can
be
tested or stored.
A second method
of
restoring the status
of
IFF
1
is
thru the execution
of
a Return
From
Non Maskable Interrupt
(RETN) instruction. Since this instruction indicates
that
the non maskable interrupt service routine
is
complete, the
contents
of
IFF
2
are now copied back into
IFF
1
,
so
that
the status
of
IFF
1
just prior
to
the acceptance
of
the non
maskable interrupt will be restored automatically.
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