106
Figure 5.0-1
is
a summary
of
the effect
of
different instructions on the two enable flip flops.
Action
IFF
1
IFF
2
CPU Reset
0 0
DI
0 0
EI
LDA,I
• •
IFF
2
~
Parity
flag
LDA,R
•
•
IFF
2
~Parity
flag
Accept
NMI
0
•
RETN
IFF
2
•
IFF2
~IFF
I
"•
" indicates no change
FIGURE
5.0
-1
INTERRUPT
ENABLE/DISABLE
FLIP
FLOPS
CPU
RESPONSE
Non Maskable
A nonmaskable interrupt will be accepted at
all
times by the CPU. When this occurs, the
CPU
ignores the next
instruction that it fetches and instead does a restart to location
0066H. Thus, it behaves exactly
as
if
it had received a
restart instruction but, it
is
to a location
that
is
not one
of
the 8 software restart locations. A restart
is
merely a call to
a specific address in page
0
of
memory.
Maskable
The
CPU
can be progr:tmmed to respond to the maskable interrupt in any one
of
three possible modes.
ModeO
This mode
is
identical to the 8080A interrupt response mode. With this mode, the interrupting device can place
any instruction on the data bus and the
CPU will execute it. Thus, the interrupting device provides the next instruction
to
be executed instead
of
the memory. Often this will be a restart instruction since the interrupting device only need
supply a single byte instruction. Alternatively, any other instruction such
as
a 3 byte call
to
any location in memory
could be executed.
The number
of
clock cycles necessary to execute this instruction
is
2 more than the normal number for the instruc-
tion. This occurs since the
CPU automatically adds 2 wait states to an interrupt response cycle to allow sufficient time
to implement an external daisy chain for priority control. Section
3.0 illustrates the detailed timing for an interrupt
response. After the application
of
RESET the CPU will automatically enter interrupt Mode 0.
Mode I
When this mode has been selected by the programmer, the
CPU will respond
to
an interrupt by executing a restart
to location
0038H. Thus the response
is
identical to that for a non maskable interrupt except that the call location
is
0338H instead
of
0066H. Another difference
is
that the number
of
cycles required to complete the restart instruction
is
2 more than normal due to the two added wait states.
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