1
22
A ROY
AS
TB
~
B ROY
"-'
B
ST
B
Z-8
0A
DATA
B
US'-,
Z-BO
A
CP U
I
ADDR
E
SS
B
US
IORQ
PIO
MT
I<"
P O
RT
DAT
A B
US
INT
BA
C'
D
CE
'oo"e'~
~
B
US
DECODER
FIGURE
7.0
-2
EXAMPLE
1/0
INTERFACE
D
D
D D
5
R
R
A
T
0 c
v
>
B v
D
1/ 0
TERM
I
NA
L
Next, the proper interrupt vector
is
loaded (refer
to
CPU Manual for details
on
the operation
of
the interrupt).
0
Inter
ru
pts are then enabled by the rising edge
of
the first M 1 after the interrupt mode word
is
set unless
that
M 1 defines
an interru
pt
acknowledge cycle. If a mask fo
ll
ows
th
e interrupt mode word, interrupts are enabled by the rising edge
of
the
fi
rst M 1 following the setting
of
th
e mask.
Data can now be transferred between the peripher
al
an
d the CP
U.
The timing for th
is
transfer
is
as
described in
Section
5.0.
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