74
IORQ
(Input/Output
Request)
RD
(Memory Read)
WR
(Memory Write)
RFSH
(Refresh)
HALT
(Halt state)
WAIT
(Wait)
INT
(Interrupt Request)
NMI
(Non Maskable
Interrupt)
Tri-state
output,
active low. The IORQ signal indicates
that
the lower half
of
the address bus
holds a valid
1/0
address for a
I/0
read or write operation. An IORQ signal
is
also generated
with
an
M
1
signal when an interrupt
is
being acknowledged
to
indicate
that
an interrupt
response vector can be placed on the data bus. Interrupt Acknowledge operations occur
during M
1
time while
1/0
operations never occur during M
1
time.
Tri-state
output,
active low. RD indicates
that
the CPU wants
to
read data from memory or
an
1/0
device. The addressed
1/0
device or memory should use this signal
to
gate data
onto
the CPU data bus.
Tri-state
output,
active low.
WR
indicates that the CPU data bus holds valid data to be
stored in the addressed memory or
1/0
device.
Output, active low. RFSH indicates
that
the lower 7 bits
of
the address bus contain a refresh
address for dynamic memories and the current MREQ signal should be used
to
do a refresh
read to all dynamic memories.
Output, active low. HALT indicates that the CPU has executed a HALT software instruction
and
is
awaiting either a non maskable or a maskable interrupt (with the mask enabled)
before operation can resume. While halted, the
CPU executes NOP's to maintain memory
refresh activity.
Input,
active low. WAIT indicates to the
Z-SOA
CPU that the addressed memory
or
I/0
devices are
not
ready for a data transfer. The CPU continues
to
enter wait states for
as
long
as
this signal
is
active. This signal allows memory
or
1/0
devices
of
any speed
to
be synchron-
ized
to
the CPU.
Input, active low. The Interrupt Request signal
is
generated
by
I/0
devices. A request will be
honored at the end
of
the current instruction
if
the internal software controlled interrupt
enable flip-flop
(IFF)
is
enabled and if the BUSRQ signal
is
not
active. When the CPU
accepts the interrupt, an acknowledge signal (IORQ during M
1
time)
is
sent
out
at the begin-
ning
of
the next instruction cycle. The CPU can respond to an interrupt
in
three different
modes.
Input, negative edge triggered. The non maskable interrupt request line has a higher priority
than INT and
is
always recognized at the end
of
the current instruction, independent
of
the
status
of
the interrupt enable flip-flop.
NMI
automatically forces the
Z-SOA
CPU to restart
to location
0066H. The program counter
is
automatically saved in the external stack
so
that
the user can return
to
the program
that
was interrupted. Note
that
continuous WAIT cycles
can prevent the current instruction from ending, and that a
BUSRQ will override a NMI.
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