76
3.0 TIMING
The Z-80A CPU executes instructions by stepping through a very precise set
of
a few basic operations. These
include:
Memory read or write
1/0 device read or write
Interrupt acknowledge
All instructions are merely a series
of
these basic operations. Each
of
these basic operations can take from three
to
six clock periods
to
complete or they can be lengthened
to
synchronize the CPU
to
the speed
of
external devices. The
basic clock periods are referred to
as
T cycles and the basic operations are referred
to
as
M (for machine) cycles. Figure
3.0-0 illustrates how a typical instruction will be merely a series
of
specific
MandT
cycles. Notice that this instruction
consists
of
three machine cycles
(M
1,
M2
and M3). The first machine cycle
of
any instruction
is
a fetch cycle which
is
four,
five
or six T cycles long (unless lengthened by the wait signal which will be fully described in the next section).
The fetch cycle
(M
1)
is
used
to
fetch the
OP
code
of
the next instruction
to
be executed. Subsequent machine cycles
move data between the
CPU and memory or 1/0 devices and they may have anywhere from three to
five
T cycles (again
they may be lengthened by wait states to synchronize the external devices
to
the CPU). The following paragraphs des-
cribe the timing which occurs within any
of
the basic machine cycles.
T Cycle
Machine
Cycle
Ml
(OP Code F
etc
h)
M2
(Memory Re
ad)
I
nstruction
C
yc
le
M3
(Memory
Writ
e)
BASIC CPU
TIMING
EXAMPLE
FIGURE
3.0-0
All CPU timing can be broken down into a
few
very simple timing diagrams
as
shown in Figure 3.0
-1
through 3.0-7.
These diagrams show the following basic operations wi
th
and without wait states (wait states a
re
added to synchronize
the
CPU
to slow memory or
I/0
devices).
3
.0-1. Instruction
OP
code fetch
(M
1 cycle)
3.0
-2
. Memory data read or write cycles
3.0-3. 1
/0
read or write cycles
3.0-4. Bus Request/Acknowledge Cycle
3.0-5.
Interrupt Request/Acknowledge Cycle
3.0-6.
Non maskable Interrupt Request/Acknowledge Cycle
3.0-7.
Exit from a HALT instruction
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