Sharp MZ-80B - Page 87

80
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*
Ta Tl
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AO - A7
X
PORT ADDRESS
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IORQ
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IN
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Cycle
RD
DATA BUS
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C yc le
Tl
-
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AO - A7
X
IORQ
DATA BUS
RD
-- ----
--
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DATA BUS
WR
INPUT OR OUTPUT CYCLES
FIGURE 3.0-3
*
T2 Tw
Tw
~ ~
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PORT ADDRESS
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r-----
-_\.__J~= ;_]-\_~-=
-----
OUT
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* Automatically inserted WAIT state
INPUT OR OUTPUT CYCLES WITH WAIT STATES
FIGURE 3.0-3A
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CYC LE
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WRITE
CYCLE