Sinclair ZX Spectrum Service Manual
Spectrum For Everyone https://spectrumforeveryone.com/
5
1.2 ARCHITECTURE
The architecture of the Spectrum 128 shown in Figure 1.1 is typical of many microcomputer systems in
that it comprises of a single microprocessor chip (in this case a Z80A or u780), a read only memory
(ROM), a paged random-access memory (RAM) and an input-output section. The latter handles the
keyboard input, tape and TV display functions using the logic gate array (ULA IC1), and the keypad input,
sound and RS232/MIDI interfaces using the sound generator circuit IC32.
The analogue circuits (not shown) generate the 17.7 MHz master clock, and process the RGB colour
monitor and sound signals. The resultant outputs are suitable for use with colour (RGB) or black and
white monitors, and domestic UHF colour television receivers. A modulated sound carrier is output with
the composite video.
The computer is built on a single printed circuit board which also includes a regulated power supply fed
from and external 9V power pack. The keyboard matrix is part of the upper case assembly and is
connected to the board via two ribbon cables KB1 and KB2. A digital keypad is also provided, connected
via a flexible cable. It can be used as a games controller or calculator pad and has special function keys
for use with the full screen editor. An in-built peripheral interface controller (PIC) performs the keypad
scanning routines and delivers an output to the Z80 on demand.
1.3 Z80A CPU
The Z80A is an 8-bit single chip central processing unit (CPU). It is clocked at 3.5 MHz from a divide of an
external source controlled by the logic gate array (ULA) and has a standard three bus input/output
arrangement. These buses are the Data Bus, Address Bus and Control Bus respectively.
Data Bus: D7-D0 constitutes an 8-bit bi-directional data bus with active high, tri-state input/outputs. It is
used for data exchanges with the memory, sound chip and the ULA.
Address Bus: A15-A0 constitutes a 16-bit address bus with active high, tri-state outputs. The address bus
provides the address for memory data exchanges and for data exchanges with the ULA. It is also used
during the interrupt routine (see below) when scanning the keyboard matrix.
Control Bus: The control bus is a collection of individual signals which generally organise the flow of data
on the address and data buses. The block diagram only shows five of these signals although others of
minor importance are made available at the expansion port (see Figure 1.5 for details).
Starting with memory request (/MREQ), this signal is active low indicating when the address bus holds a
valid address for a memory read or memory write operation. Input/output request (/IORQ) is also active
low but indicates when the address bus holds a valid I/O address for I/O read/write operations.
The read and write signals (/RD and /WR) are active low, and one or other is active indicating that the
CPU wants to read or write to a memory location or I/O device. All the control signals discussed so far
are active low, tri-state outputs.
The last control signal described here is the maskable interrupt (/INT). This input is active low and is
generated by the ULA once every 20ms. Each time it is received the CPU ‘calls’ the ‘maskable interrupt’
routine during which the real-time clock is incremented and the keyboard and keypad scanned.
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