Sinclair ZX Spectrum 128 Service Manual

Sinclair ZX Spectrum Service Manual
Spectrum For Everyone https://spectrumforeveryone.com/
8
ZA15 = ZA14 = 0: These bits select the first 16K of Z80 address space beginning at 0000
H
, and result in
the PAL generating ULA15 = ULA14 = 0. These are decoded by the ULA (IC1) to produce a signal /ROMCS
enabling the ROM IC5. A13-A0 on the Z80 address bus provide the instruction address, bank register bit
4 determines whether the upper or lower 16K of ROM is accessed.
ZA15 = 0, ZA14 = 1: These bits select the RAM page located in the second 16K of the Z80 address space
beginning at 4000
H
and result in the PAL generating ULA15 = VA15 = 0 and ULA14 = VA14 = 1. The ULA
lines signal an access of the contended RAM area and prompt IC1 to assert the /DRAS, /CAS and
/DRAMWE lines controlling the read/write operation. At the same time, ULA15 inhibits the /CAS output
from IC27 preventing any access to the uncontended RAM area.
The 2:1 data selector IC30 supplies the most significant row and column address bits to the contended
RAM as DMA7, first selecting the row address VA14 = 1 while /DRAS is low and the column address bit
VA15 = 0 when it returns high. This combination selects the second 16K bank of RAM in the contended
area, allowing DMA6 – DMA0 to access locations in page 5 used for the standard screen display.
ZA15 = 1, ZA14 = 0: These bits select the RAM page appearing in the third 16K of the Z80 address space
beginning at C000
H
, and result in the PAL generating ULA15 = UA15 = 1 and ULA14 = UA15 = 0. The ULA
lines signal an access to the uncontended RAM area and enable IC27 to assert the /CAS line which
together with /RAS (/MREQ) and /WR control the read/write operation. (Access control lines for the
contended RAM area generated by IC1 i.e. /CAS, /DRAS and /DRAMWE, are not asserted at this time).
VA15 and VA14 respectively supply the most significant row and column address bits for the
uncontended RAM area as MA7 and select the second 16K bank of RAM allowing MA6-MA0 to access
locations in page 2.
ZA15 = ZA14 = 1: These bits select the RAM page appearing in the top 16K of the Z80 address space
beginning at C000
H
. The bits together with B2-B0 from the bank register IC31 are decoded by the PAL to
select any page from the RAM according to the setting of the supplementary address line pairs. For the
uncontended RAM space ULA15 is always high allowing IC27 to control read/write operations. UA15,14
assume one of four possible states reflecting the state of B1, B0 and select a page in the range 0-3. For
contended RAM accesses ULA15 is always low allowing IC1 to control the read/write operations, and the
data selector IC30 to deliver the most significant row and column address bits VA14.15. The latter also
assume one of four states and since B2 is set, selects a page in the range 4-7.
1.4.1 Read/Write Operations and Bus Arbitration
The following description should be read in conjunction with the circuit diagram given in Figure 1.5.
Read Only Memory (IC5): The physical ROM is a 32K byte device, but appears in the Z80 address space
as two separate 16K ROM's. ROM 1 is the old 48K Spectrum ROM (slightly modified) and is selected
when bank register bit 4 sets address A14. ROM 0 is the new Spectrum 128 ROM and is selected when
bit 4 is clear. CPU accesses occur during memory read cycles when the Z80 asserts /MREQ and loads the
address bus A13-A0. /MREQ enables the ROM outputs onto the data bus D7-D0, /ROMCS decoded from
ZA14.15 (see para. 4.7) selects the chip.

Sinclair ZX Spectrum 128 Specifications

General

Brand	Sinclair
Model	ZX Spectrum 128
Category	Desktop
Language	English