— 55 —
Pin No.
31
32
33
34
35
36
37
38
39
40
41
42
43
44
I/O
I
I
I
O
I
—
—
I
I
I
I
I
I
O
Description
Rch analog negative input pin
Rch analog positive input pin
Negative voltage reference input pin, AVSS (Connected to ground)
Common voltage output pin, AVDD/2
Large external capacitor is used to reduce power-supply noise
Positive voltage reference input pin, AVDD
Analog power supply pin
Analog ground pin
X’tal input pin (Not used)
External master clock input pin if XTS = “L”
Parallel/serial select pin
“L”: serial control mode, “H”: parallel control mode (Connected to ground)
Chip select pin in serial mode
Control data clock pin in serial mode
Control data input in serial mode
Control data output pin in serial mode
Pin Name
RIN–
RIN+
VREFL
VCOM
VREFH
A. 5V
A. GND
XTI
MCLKI
S/P
CS
CCLK
CDTI
CDTO
If pins TEST, ICKS0, ICKS1, PD, S/P, DFS, DEM0, DEM1, CAD0, CAD1, S/M, MCLK, SDOS are not driven, then TEST, ICKS0, ICKS1, CAD0, CAD1,
must be tied to either AVSS or AVDD. PD, S/P, DFS, DEM0, DEM1, S/M, MCLK, SDOS must be tied to either DVSS or DVDD.
w
w
w
.
x
i
a
o
y
u
1
6
3
.
c
o
m
Q
Q
3
7
6
3
1
5
1
5
0
9
9
2
8
9
4
2
9
8
T
E
L
1
3
9
4
2
2
9
6
5
1
3
9
9
2
8
9
4
2
9
8
0
5
1
5
1
3
6
7
3
Q
Q
TEL 13942296513 QQ 376315150 892498299
TEL 13942296513 QQ 376315150 892498299
http://www.xiaoyu163.com
http://www.xiaoyu163.com
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