Sony STR-KM22 - Page 56

STR-KM22/KM55/KM77
56
HDMI BOARD (1/2) IC3009 SII9535CTUC (HDMI TRANSCEIVER)
Pin No. Pin Name I/O Description
1 SCLK_GPIO9 I/O SPI Clock/Programmable GPIO 9.
2 SCK0_IN_GPIO5 I/O I2S Serial Clock Input/Programmable GPIO 5.
3 SD0_IN/SPDIF_IN I 2S Serial Data Input/S/PDIF Input.
4
WS0_IN_GPIO6
I/O I2S Word Select Input/Programmable GPIO 6.
5 R0XC– I HDMI Receiver Port 0 TMDS Input Clock Pair.
6 R0XC+ I HDMI Receiver Port 0 TMDS Input Clock Pair.
7 R0X0– I HDMI Receiver Port 0 TMDS Input Data Pairs.
8
R0X0
+
I HDMI Receiver Port 0 TMDS Input Data Pairs.
9 R0X1– I HDMI Receiver Port 0 TMDS Input Data Pairs.
10 R0X1+ I HDMI Receiver Port 0 TMDS Input Data Pairs.
11 R0X2– I HDMI Receiver Port 0 TMDS Input Data Pairs.
12 R0X2+ I HDMI Receiver Port 0 TMDS Input Data Pairs.
13 CVDD10 - Digital Core Potential.
14 AVDD10 - TMDS Receiver Core VDD.
15 AVDD33 -
TMDS Core VDD. AVDD33 should be isolated from other system supplies to prevent leakage
from the source device through the TMDS input pins. AVDD33 should not be used to power
other system components that can be adversely affected by such leakage.
16 R1XC– I HDMI Receiver Port 1 TMDS Input Clock Pair.
17 R1XC+ I HDMI Receiver Port 1 TMDS Input Clock Pair.
18 R1X0– I HDMI Receiver Port 1TMDS Input Data Pairs.
19 R1X0+ I HDMI Receiver Port 1TMDS Input Data Pairs.
20 R1X1– I HDMI Receiver Port 1TMDS Input Data Pairs.
21 R1X1+ I HDMI Receiver Port 1TMDS Input Data Pairs.
22 R1X2– I HDMI Receiver Port 1TMDS Input Data Pairs.
23
R1X2+
I HDMI Receiver Port 1TMDS Input Data Pairs.
24 R2XC– I HDMI Receiver Port 2 TMDS Input Clock Pair.
25 R2XC+ I HDMI Receiver Port 2 TMDS Input Clock Pair.
26 R2X0– I HDMI Receiver Port 2 TMDS Input Data Pairs.
27 R2X0+ I HDMI Receiver Port 2 TMDS Input Data Pairs.
28
R2X1–
I HDMI Receiver Port 2 TMDS Input Data Pairs.
29
R2X1+
I HDMI Receiver Port 2 TMDS Input Data Pairs.
30 R2X2– I HDMI Receiver Port 2 TMDS Input Data Pairs.
31 R2X2+ I HDMI Receiver Port 2 TMDS Input Data Pairs.
32 CVDD10 - Digital Core Potential.
33 AVDD10 - TMDS Receiver Core VDD.
34
AVDD33
-
TMDS Core VDD. AVDD33 should be isolated from other system supplies to prevent leakage
from the source device through the TMDS input pins. AVDD33 should not be used to power
other system components that can be adversely affected by such leakage.
35 R3XC– I HDMI Receiver Port 3 TMDS Input Clock Pair.
36
R3XC+ I HDMI Receiver Port 3 TMDS Input Clock Pair.
37
R3X0–
I HDMI Receiver Port 3 TMDS Input Data Pairs.
38 R3X0+ I HDMI Receiver Port 3 TMDS Input Data Pairs.
39 R3X1– I HDMI Receiver Port 3 TMDS Input Data Pairs.
40 R3X1+ I HDMI Receiver Port 3 TMDS Input Data Pairs.
41
R3X2–
I HDMI Receiver Port 3 TMDS Input Data Pairs.
42 R3X2+ I HDMI Receiver Port 3 TMDS Input Data Pairs.
43 RESET_N I
External reset. Active LOW. Can be pulled to any 3.3 V supply. When main power is not pro-
vided to the system, the microcontroller must present a high-impedance of at least 100 kΩ to
RESET#.
44 CI2CA_TPWR I/O
I2C Slave Address Input/Transmit Power Sense Output. During Power-on-Reset (POR), this
pin is used as an input to latch the I2C subaddress. The level on this pin is latched when the
POR transitions from the asserted state to the deasserted state.After completion of POR, this
pin is used as the TPWR output. A register setting can change this pin to show if the active
port is receiving a TMDS clock.
45
INT
O Interrupt Output. This is an open-drain output and requires an external pull-up resistor.