ST NUCLEO-WB55RG STM32WB

UM2819
Embedded ST-LINK/V2-1
UM2819 - Rev 1
page 18/37
7.4.7 JP5 multi‑function jumper
The JP5 multi‑function jumper can connect ST-LINK/V2-1 to STM32WB55RG. It is located between the level
shifter and the SoC. It is referenced to the VDD domain (STM32WB55RG supply voltage domain).
Figure 11. Interconnection bloc diagram between STM32WB55RG and ST-LINK/V2-1
ST Restricted
JP5
Level Shifter
SWD/NRST/UART
(VDD domain)
SWD/NRST/UART
(VDD domain)
SWD/NRST/UART
(3V3_STLINK
domain)
STLINK V2.1
STM32WB55RG
U7
VDD 3V3_STLINK
1V8<VDD<3V3
Table 7. Multi-function jumper pinout description
STM32WB55RG
JP5
STM32F103 (ST-LINK)
GND
1-2
GND
NRST (pin 7)
3-4
T_NRST (PB0/pin 18)
SWDIO (PA13/pin 39)
5.6
T_SWDIO (PB12-PB14/pin 25-pin 27)
SWCLK (PA14/pin 41)
7-8
T_SWCLK (PA5-PB13/pin 15-pin 26)
SWO (PB3/pin 43)
9-10
T_SWO (PA10/pin 31)
VDD
11-12
T_VDD
USART1 TX (PA9/pin 18)
13-14
STLINK_RX: UART2 RX (PA3/pin 13)
USART1 RX (PA10/pin 36)
15-16
STLINK_TX: UART2 TX (PA2/pin 12)