The Cortex-M4 processor PM0214
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2.3.7 Exception entry and return
Descriptions of exception handling use the following terms:
Exception entry
Exception entry occurs when there is a pending exception with sufficient priority and either:
• The processor is in Thread mode
• The new exception is of higher priority than the exception being handled, in which case
the new exception preempts the original exception.
When one exception preempts another, the exceptions are nested.
Sufficient priority means the exception has more priority than any limits set by the mask
registers. For more information see Exception mask registers on page 23. An exception with
less priority than this is pending but is not handled by the processor.
When the processor takes an exception, unless the exception is a tail-chained or a late-
arriving exception, the processor pushes information onto the current stack. This operation
is referred as stacking and the structure of eight data words is referred as stack frame.
When using floating-point routines, the Cortex-M4 processor automatically stacks the
architected floating-point state on exception entry. Figure 12 on page 43 shows the Cortex-
M4 stack frame layout when floating-point state is preserved on the stack as the result of an
interrupt or an exception. Where stack space for floating-point state is not allocated, the
Preemption When the processor is executing an exception handler, an exception can
preempt the exception handler if its priority is higher than the priority of the
exception being handled. See Section 2.3.6: Interrupt priority grouping for
more information about preemption by an interrupt.
When one exception preempts another, the exceptions are called nested
exceptions. See Exception entry on page 42 more information.
Return This occurs when the exception handler is completed, and:
• There is no pending exception with sufficient priority to be serviced
• The completed exception handler was not handling a late-arriving
exception.
The processor pops the stack and restores the processor state to the state it
had before the interrupt occurred. See Exception return on page 44 for more
information.
Tail-chaining This mechanism speeds up exception servicing. On completion of an
exception handler, if there is a pending exception that meets the
requirements for exception entry, the stack pop is skipped and control
transfers to the new exception handler.
Late-arriving This mechanism speeds up preemption. If a higher priority exception occurs
during state saving for a previous exception, the processor switches to
handle the higher priority exception and initiates the vector fetch for that
exception. State saving is not affected by late arrival because the state saved
is the same for both exceptions. Therefore the state saving continues
uninterrupted. The processor can accept a late arriving exception until the
first instruction of the exception handler of the original exception enters the
execute stage of the processor. On return from the exception handler of the
late-arriving exception, the normal tail-chaining rules apply.
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