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ST STM32F4 Series

ST STM32F4 Series
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December 2019 PM0214 Rev 9 1/262
1
PM0214
Programming manual
STM32 Cortex
®
-M4 MCUs and MPUs programming manual
Introduction
This programming manual provides information for application and system-level software
developers. It gives a full description of the STM32 Cortex
®
-M4 processor programming
model, instruction set and core peripherals. The applicable products are listed in the table
below.
The Cortex
®
-M4 processor used in STM32F3 Series, STM32F4 Series, STM32G4 Series,
STM32H7 Series, STM32L4 Series, STM32L4+ Series, STM32WB Series, STM32WL
Series and STM32MP1 Series, is a high performance 32-bit processor designed for the
microcontroller and microprocessor market. It offers significant benefits to developers,
including:
Outstanding processing performance combined with fast interrupt handling
Enhanced system debug with extensive breakpoint and trace capabilities
Efficient processor core, system and memories
Ultra-low power consumption with integrated sleep modes
Platform security
Reference documents
Available from STMicroelectronics web site www.st.com:
STM32F3 Series, STM32F4 Series, STM32G4 Series, STM32H7 Series, STM32L4
Series, STM32L4+ Series, STM32MP1 Series, STM32WB Series and STM32WL
Series datasheets
STM32F3 Series, STM32F4 Series, STM32G4 Series, STM32H7 Series, STM32L4
Series, STM32L4+ Series, STM32MP1 Series, STM32WB Series and STM32WL
Series reference manuals
Table 1. Applicable products
Type Product series
Microcontrollers
STM32F3 Series, STM32F4 Series, STM32G4 Series
, STM32H7 Series,
STM32L4 Series, STM32L4+ Series, STM32WB Series, STM32WL Series
Microprocessors STM32MP1 Series
www.st.com

Table of Contents

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ST STM32F4 Series Specifications

General IconGeneral
SeriesSTM32F4
CoreARM Cortex-M4
Clock SpeedUp to 180 MHz
Flash MemoryUp to 2 MB
RAMUp to 384 KB
Operating Voltage1.8 V to 3.6 V
DAC12-bit, up to 2 channels
TimersUp to 17 timers
Communication InterfacesUSB, CAN, SPI, I2C, USART, Ethernet
Operating Temperature-40°C to 85°C
PackageLQFP, WLCSP, BGA

Summary

Introduction to the STM32 Cortex-M4 Programming Manual

Cortex-M4 Processor Features and Benefits

Summarizes key advantages: outstanding performance, enhanced debug, efficient core, low power, and security.

Reference Documents for STM32 Cortex-M4

Lists datasheets and reference manuals available from STMicroelectronics website for further details.

About this document

Typographical Conventions Used

Explains conventions for highlighting important notes, cross-references, and code elements.

Abbreviations for Registers

Lists common abbreviations used in register descriptions, such as (rw), (r), and (w).

STM32 Cortex-M4 Processor and Core Peripherals Overview

Introduces the Cortex-M4 processor, its architecture, and integrated core peripherals.

The Cortex-M4 Processor

Cortex-M4 Programmers Model

Describes processor modes, privilege levels, execution states, and stack usage.

Cortex-M4 Memory Model

Explains the memory map, access behavior, and bit-banding features.

Cortex-M4 Exception Model

Covers exception states, types, handlers, priorities, and grouping mechanisms.

The STM32 Cortex-M4 Instruction Set

Instruction Set Summary and Syntax

Lists supported instructions, syntax conventions, and flexible operand usage.

Memory Access Instructions

Details instructions for loading and storing data from memory.

General Data Processing Instructions

Covers arithmetic, logical, shift, and data manipulation instructions.

Multiply and Divide Instructions

Explains signed/unsigned multiply, accumulate, divide, and saturation instructions.

Saturating Instructions

Describes instructions performing saturation arithmetic on signed/unsigned values.

Core Peripherals

Nested Vectored Interrupt Controller (NVIC)

Details the NVIC's interrupt handling, priority levels, and registers.

System Control Block (SCB) Registers

Explains SCB registers for system control, configuration, and exception reporting.

SysTick Timer (STK) Functionality

Describes the SysTick timer for system timing and RTOS tick generation.

Document Revision History

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