ST STM32F4 Series User Manual

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PM0214 The STM32 Cortex-M4 instruction set
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; from R5, saturates to 32 bits, writes to R0.
3.7.6 UQASX and UQSAX
Saturating Add and Subtract with Exchange and Saturating Subtract and Add with
Exchange, unsigned.
Syntax
op{cond} {Rd}, Rm, Rn
Where:
• op’ is one of:
UQASX Add and Subtract with Exchange and Saturate.
UQSAX Subtract and Add with Exchange and Saturate.
• ‘cond’ is an optional condition code (see Conditional execution on page 65)
• ‘Rd’ is the destination register.
• ‘Rn, Rm’ are registers holding the first and second operands.
Operation
The UQASX instruction:
1. Adds the bottom halfword of the source operand with top halfword of second operand.
2. Subtracts the bottom halfword of the second operand from the top highword of the first
operand.
3. Saturates the results of the sum and writes a 16-bit unsigned integer in the range
4. 0 ≤ x ≤ 2
16
– 1, where x equals 16, to the top halfword of the destination register.
5. Saturates the result of the subtraction and writes a 16-bit unsigned integer in the range
0
≤ x ≤ 2
16
– 1, where x equals 16, to the bottom halfword of the destination register.
The UQSAX instruction:
1. Subtracts the bottom halfword of second operand from top highword of first operand.
2. Adds the bottom halfword of the first operand with the top halfword of the second
operand.
3. Saturates the result of the subtraction and writes a 16-bit unsigned integer in the range
0
≤ x ≤ 2
16
– 1, where x equals 16, to the top halfword of the destination register.
4. Saturates the results of the addition and writes a 16-bit unsigned integer in the range 0
≤ x ≤ 2
16
– 1, where x equals 16, to the bottom halfword of the destination register.
Restrictions
Do not use SP and do not use PC.
Condition flags
These instructions do not affect the condition code flags.
Examples
UQASX R7, R4, R2 ; Adds top halfword of R4 with bottom halfword of R2,
; saturates to 16 bits, writes to top halfword of R7
; Subtracts top halfword of R2 from bottom halfword of

ST STM32F4 Series Specifications

General

Series	STM32F4
Core	ARM Cortex-M4
Clock Speed	Up to 180 MHz
Flash Memory	Up to 2 MB
RAM	Up to 384 KB
Operating Voltage	1.8 V to 3.6 V
DAC	12-bit, up to 2 channels
Timers	Up to 17 timers
Communication Interfaces	USB, CAN, SPI, I2C, USART, Ethernet
Operating Temperature	-40°C to 85°C
Package	LQFP, WLCSP, BGA

Summary

Introduction to the STM32 Cortex-M4 Programming Manual

Cortex-M4 Processor Features and Benefits

Summarizes key advantages: outstanding performance, enhanced debug, efficient core, low power, and security.

Reference Documents for STM32 Cortex-M4

Lists datasheets and reference manuals available from STMicroelectronics website for further details.

About this document

Typographical Conventions Used

Explains conventions for highlighting important notes, cross-references, and code elements.

Abbreviations for Registers

Lists common abbreviations used in register descriptions, such as (rw), (r), and (w).

STM32 Cortex-M4 Processor and Core Peripherals Overview

Introduces the Cortex-M4 processor, its architecture, and integrated core peripherals.

The Cortex-M4 Processor

Cortex-M4 Programmers Model

Describes processor modes, privilege levels, execution states, and stack usage.

Cortex-M4 Memory Model

Explains the memory map, access behavior, and bit-banding features.

Cortex-M4 Exception Model

Covers exception states, types, handlers, priorities, and grouping mechanisms.

The STM32 Cortex-M4 Instruction Set

Instruction Set Summary and Syntax

Lists supported instructions, syntax conventions, and flexible operand usage.

Memory Access Instructions

Details instructions for loading and storing data from memory.

General Data Processing Instructions

Covers arithmetic, logical, shift, and data manipulation instructions.

Multiply and Divide Instructions

Explains signed/unsigned multiply, accumulate, divide, and saturation instructions.

Saturating Instructions

Describes instructions performing saturation arithmetic on signed/unsigned values.

Core Peripherals

Nested Vectored Interrupt Controller (NVIC)

Details the NVIC's interrupt handling, priority levels, and registers.

System Control Block (SCB) Registers

Explains SCB registers for system control, configuration, and exception reporting.

SysTick Timer (STK) Functionality

Describes the SysTick timer for system timing and RTOS tick generation.

Document Revision History