ST STM32F3 Series

March 2020 PM0214 Rev 10 1/262
1
PM0214
Programming manual
STM32 Cortex
®
-M4 MCUs and MPUs programming manual
Introduction
This programming manual provides information for application and system-level software
developers. It gives a full description of the STM32 Cortex
®
-M4 processor programming
model, instruction set and core peripherals. The applicable products are listed in the table
below.
The Cortex
®
-M4 processor used in STM32F3 Series, STM32F4 Series, STM32G4 Series,
STM32H745/755 and STM32H747/757 Lines, STM32L4 Series, STM32L4+ Series,
STM32WB Series, STM32WL Series and STM32MP1 Series, is a high performance 32-bit
processor designed for the microcontroller and microprocessor market. It offers significant
benefits to developers, including:
• Outstanding processing performance combined with fast interrupt handling
• Enhanced system debug with extensive breakpoint and trace capabilities
• Efficient processor core, system and memories
• Ultra-low power consumption with integrated sleep modes
• Platform security
Reference documents
Available from STMicroelectronics web site www.st.com:
• Datasheets of STM32F3 Series, STM32F4 Series, STM32G4 Series, STM32H745/755
and STM32H747/757 Lines, STM32L4 Series, STM32L4+ Series, STM32MP1 Series,
STM32WB Series and STM32WL Series
• Reference manuals of STM32F3 Series, STM32F4 Series, STM32G4 Series,
STM32H745/755 and STM32H747/757 Lines, STM32L4 Series, STM32L4+ Series,
STM32MP1 Series, STM32WB Series and STM32WL Series
Table 1. Applicable products
Type Product Series and Lines
Microcontrollers
STM32F3 Series, STM32F4 Series, STM32G4 Series, STM32L4 Series,
STM32L4+ Series, STM32WB Series, STM32WL Series
STM32H745/755 and STM32H747/757 Lines
Microprocessors STM32MP1 Series
www.st.com

ST STM32F3 Series Specifications

General

Series	STM32F3
Core	ARM Cortex-M4
Max CPU Frequency	72 MHz
Operating Voltage	2.0 V to 3.6 V
GPIO Pins	Up to 80
Timers	Advanced-control, general-purpose, basic timers
ADC	12-bit
DAC	12-bit
Communication Interfaces	USART, SPI, I2C, CAN, USB
Operating Temperature	-40°C to 85°C
Package	LQFP, UFQFPN, WLCSP

Summary

Introduction

1 About this document

1.1 Typographical conventions

Conventions used in the document for formatting text and code elements.

1.2 List of abbreviations for registers

Abbreviations used in register descriptions.

1.3 About the STM32 Cortex-M4 processor and core peripherals

Overview of the processor's features and integrated peripherals.

2 The Cortex-M4 processor

2.1 Programmers model

Describes the programmer's model, processor modes, privilege levels, and stacks.

2.2 Memory model

Details the processor memory map, access behavior, and bit-banding features.

2.3 Exception model

Explains the exception model, states, types, handlers, and priorities.

2.4 Fault handling

Details fault types, escalation, status registers, and lockup.

2.5 Power management

Describes mechanisms for entering and waking up from sleep modes.

3 The STM32 Cortex-M4 instruction set

3.1 Instruction set summary

Overview of the instruction set and supported instructions.

3.2 CMSIS intrinsic functions

CMSIS intrinsic functions for generating Cortex-M4 instructions.

3.3 About the instruction descriptions

Explains how instruction descriptions are presented in the document.

3.4 Memory access instructions

Details instructions for accessing memory.

3.5 General data processing instructions

Covers general-purpose data processing instructions.

3.6 Multiply and divide instructions

Describes instructions for multiplication and division operations.

3.7 Saturating instructions

Explains instructions that perform saturating arithmetic.

3.8 Packing and unpacking instructions

Instructions for packing and unpacking data.

3.9 Bitfield instructions

Instructions for operating on bitfields within registers.

3.10 Floating-point instructions

Instructions for floating-point operations using the FPU.

3.11 Miscellaneous instructions

Other Cortex-M4 instructions not categorized elsewhere.

4 Core peripherals

4.1 About the STM32 Cortex-M4 core peripherals

Overview of core peripherals and their memory map in the PPB.

4.2 Memory protection unit (MPU)

Details the MPU's functionality for memory protection and region management.

4.3 Nested vectored interrupt controller (NVIC)

Describes the NVIC's support for interrupts, priorities, and tail-chaining.

4.4 System control block (SCB)

Provides system implementation info and control for exceptions.

4.5 SysTick timer (STK)

Details the SysTick timer, its registers, and usage hints.

4.6 Floating point unit (FPU)

Explains the FPU's functionality, registers, and enabling.

5 Revision history