ST STM32F3 Series User Manual

The STM32 Cortex-M4 instruction set PM0214
104/262 PM0214 Rev 10
UHSAX R0, R3, R5 ; Subtracts bottom halfword of R5 from top halfword of
; R3 and writes halved result to top halfword of R0
; Adds top halfword of R5 to bottom halfword of R3 and
; writes halved result to bottom halfword of R0.
3.5.20 UHSUB16 and UHSUB8
Unsigned Halving Subtract 16 and Unsigned Halving Subtract 8
Syntax
op{cond}{Rd,} Rn, Rm
Where:
• op is any of the following:
UHSUB16: Performs two unsigned 16-bit integer additions, halves the results, and
writes the results to the destination register.
UHSUB8: Performs four unsigned 8-bit integer additions, halves the results, and writes
the results to the destination register.
• ‘cond’ is an optional condition code (see Conditional execution on page 65).
• ‘Rd’ is the destination register.
• ‘Rn’ is the first register holding the operand.
• ‘Rm’ is the second register holding the operand.
Operation
Use these instructions to add 16-bit and 8-bit data and then to halve the result before writing
the result to the destination register:
The UHSUB16 instruction:
1. Subtracts each halfword of the second operand from the corresponding halfword of the
first operand.
2. Shuffles each halfword result to the right by one bit, halving the data.
3. Writes each unsigned halfword result to corresponding halfword in destination register.
The UHSUB8 instruction:
1. Subtracts each byte of second operand from the corresponding byte of the first
operand.
2. Shuffles each byte result by one bit to the right, halving the data.
3. Writes the unsigned byte results to the corresponding byte of the destination register.
Restrictions
Do not use SP and do not use PC.
Condition flags
These instructions do not change the flags.
Examples
UHSUB16 R1, R0 ; Subtracts halfwords in R0 from corresponding R1 halfword
; and writes halved result to corresponding halfword in R1

ST STM32F3 Series Specifications

General

Series	STM32F3
Core	ARM Cortex-M4
Max CPU Frequency	72 MHz
Operating Voltage	2.0 V to 3.6 V
GPIO Pins	Up to 80
Timers	Advanced-control, general-purpose, basic timers
ADC	12-bit
DAC	12-bit
Communication Interfaces	USART, SPI, I2C, CAN, USB
Operating Temperature	-40°C to 85°C
Package	LQFP, UFQFPN, WLCSP

Summary

Introduction

1 About this document

1.1 Typographical conventions

Conventions used in the document for formatting text and code elements.

1.2 List of abbreviations for registers

Abbreviations used in register descriptions.

1.3 About the STM32 Cortex-M4 processor and core peripherals

Overview of the processor's features and integrated peripherals.

2 The Cortex-M4 processor

2.1 Programmers model

Describes the programmer's model, processor modes, privilege levels, and stacks.

2.2 Memory model

Details the processor memory map, access behavior, and bit-banding features.

2.3 Exception model

Explains the exception model, states, types, handlers, and priorities.

2.4 Fault handling

Details fault types, escalation, status registers, and lockup.

2.5 Power management

Describes mechanisms for entering and waking up from sleep modes.

3 The STM32 Cortex-M4 instruction set

3.1 Instruction set summary

Overview of the instruction set and supported instructions.

3.2 CMSIS intrinsic functions

CMSIS intrinsic functions for generating Cortex-M4 instructions.

3.3 About the instruction descriptions

Explains how instruction descriptions are presented in the document.

3.4 Memory access instructions

Details instructions for accessing memory.

3.5 General data processing instructions

Covers general-purpose data processing instructions.

3.6 Multiply and divide instructions

Describes instructions for multiplication and division operations.

3.7 Saturating instructions

Explains instructions that perform saturating arithmetic.

3.8 Packing and unpacking instructions

Instructions for packing and unpacking data.

3.9 Bitfield instructions

Instructions for operating on bitfields within registers.

3.10 Floating-point instructions

Instructions for floating-point operations using the FPU.

3.11 Miscellaneous instructions

Other Cortex-M4 instructions not categorized elsewhere.

4 Core peripherals

4.1 About the STM32 Cortex-M4 core peripherals

Overview of core peripherals and their memory map in the PPB.

4.2 Memory protection unit (MPU)

Details the MPU's functionality for memory protection and region management.

4.3 Nested vectored interrupt controller (NVIC)

Describes the NVIC's support for interrupts, priorities, and tail-chaining.

4.4 System control block (SCB)

Provides system implementation info and control for exceptions.

4.5 SysTick timer (STK)

Details the SysTick timer, its registers, and usage hints.

4.6 Floating point unit (FPU)

Explains the FPU's functionality, registers, and enabling.

5 Revision history