ST STM32F3 Series User Manual

PM0214 Rev 10 67/262
PM0214 The STM32 Cortex-M4 instruction set
261
Condition code suffixes
The instructions that can be conditional have an optional condition code, shown in syntax
descriptions as
{cond} . Conditional execution requires a preceding IT instruction. An
instruction with a condition code is only executed if the condition code flags in the APSR
meet the specified condition. Table 24 shows the condition codes to use.
You can use conditional execution with the
IT instruction to reduce the number of branch
instructions in code.
Table 24 also shows the relationship between condition code suffixes and the N, Z, C, and V
flags.
Specific example 1: Absolute value shows the use of a conditional instruction to find the
absolute value of a number. R0 = ABS(R1).
Specific example 1: Absolute value
MOVSR0, R1; R0 = R1, setting flags
IT MI ; IT instruction for the negative condition
RSBMIR0, R1, #0; If negative, R0 = -R1
Specific example 2: Compare and update value shows the use of conditional instructions to
update the value of R4 if the signed value R0 and R2 are greater than R1 and R3
respectively.
Specific example 2: Compare and update value
CMP R0, R1 ; compare R0 and R1, setting flags
ITT GT ; IT instruction for the two GT conditions
Table 24. Condition code suffixes
Suffix Flags Meaning
EQ Z = 1 Equal
NE Z = 0 Not equal
CS or HS C = 1 Higher or same, unsigned ≥
CC or LO C = 0 Lower, unsigned <
MI N = 1 Negative
PL N = 0 Positive or zero
VS V = 1 Overflow
VC V = 0 No overflow
HI C = 1 and Z = 0 Higher, unsigned >
LS C = 0 or Z = 1 Lower or same, unsigned
≤
GE N = V Greater than or equal, signed ≥
LT N != V Less than, signed <
GT Z = 0 and N = V Greater than, signed >
LE Z = 1 and N != V Less than or equal, signed
≤
AL Can have any value Always. This is the default when no suffix is specified.

ST STM32F3 Series Specifications

General

Series	STM32F3
Core	ARM Cortex-M4
Max CPU Frequency	72 MHz
Operating Voltage	2.0 V to 3.6 V
GPIO Pins	Up to 80
Timers	Advanced-control, general-purpose, basic timers
ADC	12-bit
DAC	12-bit
Communication Interfaces	USART, SPI, I2C, CAN, USB
Operating Temperature	-40°C to 85°C
Package	LQFP, UFQFPN, WLCSP

Summary

Introduction

1 About this document

1.1 Typographical conventions

Conventions used in the document for formatting text and code elements.

1.2 List of abbreviations for registers

Abbreviations used in register descriptions.

1.3 About the STM32 Cortex-M4 processor and core peripherals

Overview of the processor's features and integrated peripherals.

2 The Cortex-M4 processor

2.1 Programmers model

Describes the programmer's model, processor modes, privilege levels, and stacks.

2.2 Memory model

Details the processor memory map, access behavior, and bit-banding features.

2.3 Exception model

Explains the exception model, states, types, handlers, and priorities.

2.4 Fault handling

Details fault types, escalation, status registers, and lockup.

2.5 Power management

Describes mechanisms for entering and waking up from sleep modes.

3 The STM32 Cortex-M4 instruction set

3.1 Instruction set summary

Overview of the instruction set and supported instructions.

3.2 CMSIS intrinsic functions

CMSIS intrinsic functions for generating Cortex-M4 instructions.

3.3 About the instruction descriptions

Explains how instruction descriptions are presented in the document.

3.4 Memory access instructions

Details instructions for accessing memory.

3.5 General data processing instructions

Covers general-purpose data processing instructions.

3.6 Multiply and divide instructions

Describes instructions for multiplication and division operations.

3.7 Saturating instructions

Explains instructions that perform saturating arithmetic.

3.8 Packing and unpacking instructions

Instructions for packing and unpacking data.

3.9 Bitfield instructions

Instructions for operating on bitfields within registers.

3.10 Floating-point instructions

Instructions for floating-point operations using the FPU.

3.11 Miscellaneous instructions

Other Cortex-M4 instructions not categorized elsewhere.

4 Core peripherals

4.1 About the STM32 Cortex-M4 core peripherals

Overview of core peripherals and their memory map in the PPB.

4.2 Memory protection unit (MPU)

Details the MPU's functionality for memory protection and region management.

4.3 Nested vectored interrupt controller (NVIC)

Describes the NVIC's support for interrupts, priorities, and tail-chaining.

4.4 System control block (SCB)

Provides system implementation info and control for exceptions.

4.5 SysTick timer (STK)

Details the SysTick timer, its registers, and usage hints.

4.6 Floating point unit (FPU)

Explains the FPU's functionality, registers, and enabling.

5 Revision history