The STM32 Cortex-M4 instruction set PM0214
180/262 PM0214 Rev 10
3.11 Miscellaneous instructions
Table 36 shows the remaining Cortex-M4 instructions:
Table 36. Miscellaneous instructions
Mnemonic Brief description See
BKPT Breakpoint BKPT on page 181
CPSID Change Processor State, Disable Interrupts CPS on page 182
CPSIE Change Processor State, Enable Interrupts CPS on page 182
DMB Data Memory Barrier DMB on page 183
DSB Data Synchronization Barrier DSB on page 184
ISB Instruction Synchronization Barrier ISB on page 185
MRS Move from special register to register MRS on page 186
MSR Move from register to special register MSR on page 187
NOP No Operation NOP on page 188
SEV Send Event SEV on page 189
SVC Supervisor Call SVC on page 190
WFE Wait For Event WFE on page 191
WFI Wait For Interrupt WFI on page 192
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