The Cortex-M4 processor PM0214
24/262 PM0214 Rev 10
To access the exception mask registers use the MSR and MRS instructions, or the CPS
instruction to change the value of PRIMASK or FAULTMASK. See MRS on page 186, MSR
on page 187, and CPS on page 182 for more information.
Priority mask register
The PRIMASK register prevents the activation of all exceptions with configurable priority.
See the register summary in Table 3 on page 18 for its attributes. Figure 5 shows the bit
assignment.
Figure 5. PRIMASK bit assignment
Fault mask register
The FAULTMASK register prevents activation of all exceptions except for Non-Maskable
Interrupt (NMI). See the register summary in Table 3 on page 18 for its attributes. Figure 6
shows the bit assignment.
Figure 6. FAULTMASK bit assignment
The processor clears the FAULTMASK bit to 0 on exit from any exception handler except
the NMI handler.
Table 8. PRIMASK register bit definitions
Bits Description
Bits 31:1 Reserved
Bit 0
PRIMASK:
0: No effect
1: Prevents the activation of all exceptions with configurable priority.
Table 9. FAULTMASK register bit definitions
Bits Function
Bits 31:1 Reserved
Bit 0 FAULTMASK:
0: No effect
1: Prevents the activation of all exceptions except for NMI.
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